Power gating design for standard-cell-like structured ASICs. - Sin-Yu Chen; Rung-Bin Lin; Hui-Hsiang Tung; Kuen-Wey Lin (DATE, 2010)

Via configurable three-input lookup-tables for structured ASICs. - Yu-Chen Chen; Hou-Yu Pang; Kuen-Wey Lin; Rung-Bin Lin; Hui-Hsiang Tung; Shih-Chieh Su (ACM Great Lakes Symposium on VLSI, 2010)

Logic block and design methodology for via-configurable structured ASIC using dual supply voltages. - Ta-Kai Lin; Kuen-Wey Lin; Chang-Hao Chiu; Rung-Bin Lin (ACM Great Lakes Symposium on VLSI, 2014)

Multiple-patterning lithography-aware routing for standard cell layout synthesis. - Kuen-Wey Lin; Yih-Lang Li; Rung-Bin Lin (APCCAS, 2016)

A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points. - Kuen-Wey Lin; Yeh-Sheng Lin; Yih-Lang Li; Rung-Bin Lin (ACM Great Lakes Symposium on VLSI, 2017)

Near-future traffic evaluation based navigation for automated driving vehicles. - Kuen-Wey Lin; Yih-Lang Li; Masanori Hashimoto (Intelligent Vehicles Symposium, 2017)

Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties. - Kuen-Wey Lin; Masanori Hashimoto; Yih-Lang Li (ISQED, 2018)

A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction. - Kuen-Wey Lin; Yeh-Sheng Lin; Yih-Lang Li; Rung-Bin Lin (ACM Trans. Design Autom. Electr. Syst., 2018)