TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC. - Lei Wang 011; Hongyi Lu; Kui Dai; Zhiying Wang 003 (Asia-Pacific Computer Systems Architecture Conference, 2004)

Improving Security Architecture Development Based on Multiple Criteria Decision Making. - Fang Liu 002; Kui Dai; Zhiying Wang 003 (AWCC, 2004)

Analysis of Inter-Frame Coding Without Intra Modes in H.264. - Yun Cheng; Zhiying Wang 003; Kui Dai; Jianjun Guo (Eurographics Multimedia Workshop, 2004)

A New Technique for Program Code Compression in Embedded Microprocessor. - Ming-che Lai; Kui Dai; Li Shen 007; Zhiying Wang 003 (ICESS, 2004)

Applying multiple criteria decision making to improve security architecture development. - Fang Liu 002; Kui Dai; Zhiying Wang 003 (InfoSecu, 2004)

A network intrusion detection system based on the artificial neural networks. - Jing-Xin Wang; Zhi-Ying Wang; Kui Dai (InfoSecu, 2004)

Research on Fast Block Participation Mode Selection Algorithm in H.264. - Jianjun Guo; Kui Dai; Yun Cheng; Zhiying Wang 003 (ACIS-ICIS, 2005)

A Fast Motion Estimation Algorithm Based on Diamond and Simplified Square Search Patterns. - Yun Cheng; Kui Dai; Zhiying Wang 003; Jianjun Guo (CIARP, 2005)

Research on intra modes for inter-frame coding in H.264. - Yun Cheng; Zhiying Wang 003; Jianjun Guo; Kui Dai (CSCWD (2), 2005)

Retargetable Machine-Description System: Multi-layer Architecture Approach. - Dan Wu; Zhiying Wang 003; Kui Dai (GCC, 2005)

A Fast Motion Estimation Algorithm Based on Diamond and Triangle Search Patterns. - Yun Cheng; Zhiying Wang 003; Kui Dai; Jianjun Guo (IbPRIA (1), 2005)

Research on Fuzzy Group Decision Making in Security Risk Assessment. - Fang Liu 002; Kui Dai; Zhiying Wang 003; Jun Ma 015 (ICN (2), 2005)

Design of a Configurable Embedded Processor Architecture for DSP Functions. - Hong Yue; Ming-che Lai; Kui Dai; Zhiying Wang 003 (ICPADS (2), 2005)

Protecting Mass Data Basing on Small Trusted Agent. - Fangyong Hou; Zhiying Wang 003; Kui Dai; Yun Liu (ISPEC, 2005)

Trust-Enhanced Alteration Scenario for Universal Computer. - Jiangchun Ren; Kui Dai; Zhiying Wang 003 (PRDC, 2005)

Research on Risk Probability Estimating Using Fuzzy Clustering for Dynamic Security Assessment. - Fang Liu 002; Yong Chen; Kui Dai; Zhiying Wang 003; Zhiping Cai (RSFDGrC (2), 2005)

Design and Implementation a TPM Chip SUP320 by SOC. - Jiangchun Ren; Kui Dai; Zhiying Wang 003; Xue-mi Zhao; Yuan-man Tong (SEC, 2005)

Two New Space-Time Triple Modular Redundancy Techniques for Improving Fault Tolerance of Computer Systems. - Wei Chen 009; Rui Gong; Kui Dai; Fang Liu 002; Zhiying Wang 003 (CIT, 2006)

An Approximate Method for Performance Evaluation of Asynchronous Pipeline Rings. - Lei Wang 011; Zhiying Wang 003; Kui Dai (CIT, 2006)

A Heterogeneous Multi-core Processor Architecture for High Performance Computing. - Jianjun Guo; Kui Dai; Zhiying Wang 003 (Asia-Pacific Computer Systems Architecture Conference, 2006)

Cycle Period Analysis and Optimization of Timed Circuits. - Lei Wang 011; Zhiying Wang 003; Kui Dai (Asia-Pacific Computer Systems Architecture Conference, 2006)

Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining. - Yuan-man Tong; Zhiying Wang 003; Kui Dai; Hongyi Lu (Inscrypt, 2006)

Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy. - Wei Chen 009; Rui Gong; Fang Liu 002; Kui Dai; Zhiying Wang 003 (ESA, 2006)

A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications. - Hong Yue; Kui Dai; Zhiying Wang 003 (ESA, 2006)

Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique. - Rui Gong; Wei Chen 009; Fang Liu 002; Kui Dai; Zhiying Wang 003 (DFT, 2006)

A High Performance Heterogeneous Architecture and Its Optimization Design. - Jianjun Guo; Kui Dai; Zhiying Wang 003 (HPCC, 2006)

A Heterogeneous Embedded MPSoC for Multimedia Applications. - Hong Yue; Zhiying Wang 003; Kui Dai (HPCC, 2006)

A Novel Data-Parallel Coprocessor for Multimedia Signal Processing. - Ming-che Lai; Kui Dai; Lu Hong-yi; Zhiying Wang 003 (ICME, 2006)

Intrusion Alert Analysis Based on PCA and the LVQ Neural Network. - Jing-Xin Wang; Zhiying Wang 003; Kui Dai (ICONIP (3), 2006)

A PCA-LVQ Model for Intrusion Alert Analysis. - Jing-Xin Wang; Zhiying Wang 003; Kui Dai (ISI, 2006)

An Efficient Way to Build Secure Disk. - Fangyong Hou; Hongjun He; Zhiying Wang 003; Kui Dai (ISPEC, 2006)

A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology. - Xue-mi Zhao; Zhiying Wang 003; Hongyi Lu; Kui Dai (VLSI-SoC, 2006)

Research and Implementation of a 32-Bit Asynchronous Multiplier. - Yong Li 006; Lei Wang 011; Rui Gong; Kui Dai; Zhiying Wang 003 (J. Comput. Res. Dev., 2006)

A Low-Power Application Specific Instruction Set Processor Using Asynchronous Function Units. - Yong Li 006; Zhiying Wang 003; Kui Dai (CIT, 2007)

Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units. - Yong Li 006; Zhiying Wang 003; Xue-mi Zhao; Jian Ruan; Kui Dai (Asia-Pacific Computer Systems Architecture Conference, 2007)

An Optimal Design Method for De-synchronous Circuit Based on Control Graph. - Gang Jin; Lei Wang 011; Zhiying Wang 003; Kui Dai (APPT, 2007)

A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design. - Libo Huang; Li Shen 007; Kui Dai; Zhiying Wang 003 (IEEE Symposium on Computer Arithmetic, 2007)

A Low-Power Globally Synchronous Locally Asynchronous FFT Processor. - Yong Li 006; Zhiying Wang 003; Jian Ruan; Kui Dai (HPCC, 2007)

Latency Estimation of the Asynchronous Pipeline Using the Max-Plus Algebra. - Jian Ruan; Zhiying Wang 003; Kui Dai; Yong Li 006 (International Conference on Computational Science (4), 2007)

Security Event Management System based on Mobile Agent Technology. - Wang Jingxin; Zhiying Wang 003; Kui Dai (ISI, 2007)

The Research of an Embedded Processor Element for Multimedia Domain. - Ming-che Lai; Jianjun Guo; Lv Yasuai; Kui Dai; Zhiying Wang 003 (MCAM, 2007)

Hardware Support for Arithmetic Units of Processor with Multimedia Extension. - Libo Huang; Ming-che Lai; Kui Dai; Hong Yue; Li Shen 007 (MUE, 2007)

Template Vertical Dictionary-Based Program Compression Scheme on the TTA. - Ming-che Lai; Zhiying Wang 003; Jianjun Guo; Kui Dai; Shen Li (PATMOS, 2007)

Design and Test of Self-checking Asynchronous Control Circuit. - Jian Ruan; Zhiying Wang 003; Kui Dai; Yong Li 006 (PATMOS, 2007)

Memory System Design for a Multi-core Processor. - Jianjun Guo; Ming-che Lai; Zhengyuan Pang; Libo Huang; Fangyuan Chen; Kui Dai; Zhiying Wang 003 (CISIS, 2008)

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers. - Ming-che Lai; Zhiying Wang 003; Lei Gao; Hongyi Lu; Kui Dai (DAC, 2008)

A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors. - Rui Gong; Kui Dai; Zhiying Wang 003 (DFT, 2008)

Low-Level Component for OpenGL ES Oriented Heterogeneous Architecture with Optimization. - Xinbiao Gan; Kui Dai; Zhiying Wang 003 (ICYCS, 2008)

Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving. - Rui Gong; Kui Dai; Zhiying Wang 003 (ICYCS, 2008)

The P2P Communication Model for a Local Memory based Multi-core Processor. - Jianjun Guo; Kui Dai; Ming-che Lai; Zhiying Wang 003 (ICYCS, 2008)

Performance Bound Analysis and Retiming of Timed Circuits. - Lei Wang 011; Zhiying Wang 003; Kui Dai (ICYCS, 2008)

A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture. - Xinbiao Gan; Kui Dai; Libo Huang; Li Shen 007; Zhiying Wang 003 (MUE, 2008)

Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy. - Rui Gong; Kui Dai; Zhiying Wang 003 (PRDC, 2008)

Hierarchical memory system design for a heterogeneous multi-core processor. - Jianjun Guo; Ming-che Lai; Zhengyuan Pang; Libo Huang; Fangyuan Chen; Kui Dai; Zhiying Wang 003 (SAC, 2008)

Control flow checking and recovering based on 8051 architecture. - Rui Gong; Wei Chen 009; Fang Liu 002; Kui Dai; Zhiying Wang 003 (SAC, 2008)

A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique. - Rui Gong; Wei Chen 009; Fang Liu 002; Kui Dai; Zhiying Wang 003 (J. Electron. Test., 2008)

Implementation of OpenVG Path and Paint Algorithms on Synchronous Data Triggered Architecture with Optimization. - Sheng Ma; Libo Huang; Zhiying Wang 003; Kui Dai (NAS, 2009)

The parallel algorithm implementation of matrix multiplication based on ESCA. - Pan Chen; Kui Dai; Dan Wu 009; Jinli Rao; Xuecheng Zou (APCCAS, 2010)

A High Efficient On-Chip Interconnection Network in SIMD CMPs. - Dan Wu 009; Kui Dai; Xuecheng Zou; Jinli Rao; Pan Chen (ICA3PP (1), 2010)

New design of RF rectifier for passive UHF RFID transponders. - Dongsheng Liu; Xuecheng Zou; Kui Dai; Si-Zheng Li; Xue-Mei Hui; Yao Liu; Qiaoling Tong (Microelectron. J., 2010)

An area-efficient 5GHz/10GHz dual-mode VCO with coupled helical inductors in 0.13-UM CMOS technology. - Wanghui Zou; Xiaofei Chen; Jianming Lei; Kui Dai; Xuecheng Zou (CCECE, 2011)

Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture. - Dan Wu 009; Xuecheng Zou; Kui Dai; Jinli Rao; Pan Chen; Zhaoxia Zheng (J. Zhejiang Univ. Sci. C, 2011)

A Compact Hardware Implementation of SM3 Hash Function. - Tianyong Ao; Zhangqing He; Jinli Rao; Kui Dai; Xuecheng Zou (TrustCom, 2014)

Mac or Non-MAC: not a Problem. - Libo Huang; Li Shen 007; Yashuai Lv; Zhiying Wang 003; Kui Dai (J. Circuits Syst. Comput., 2014)

A 1-V 2.5-ppm/°C second-order compensated bandgap reference. - Meilin Wan; Zhenzhen Zhang; Kui Dai; Xuecheng Zou (ASICON, 2015)

A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks. - Meilin Wan; Zhenzhen Zhang; Wang Liao; Kui Dai; Xuecheng Zou (J. Circuits Syst. Comput., 2015)

An Invasive-Attack-Resistant PUF Based On Switched-Capacitor Circuit. - Meilin Wan; Zhangqing He; Shuang Han; Kui Dai; Xuecheng Zou (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

BFWindow: Speculatively Checking Data Property Consistency against Buffer Overflow Attacks. - Jinli Rao; Zhangqing He; Shu Xu; Kui Dai; Xuecheng Zou (IEICE Trans. Inf. Syst., 2016)

A Nonlinearity-Compensated All-MOS Voltage-to-Current Converter. - Meilin Wan; Wang Liao; Kui Dai; Xuecheng Zou (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A Novel Thyristor-Based Silicon Physical Unclonable Function. - Chuang Bai; Xuecheng Zou; Kui Dai (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor. - Jinli Rao; Tianyong Ao; Shu Xu; Kui Dai; Xuecheng Zou (IEICE Trans. Inf. Syst., 2018)

A Reliable Strong PUF Based on Switched-Capacitor Circuit. - Zhangqing He; Meilin Wan; Jie Deng; Chuang Bai; Kui Dai (IEEE Trans. Very Large Scale Integr. Syst., 2018)

ARCE: Towards Code Pointer Integrity on Embedded Processors Using Architecture-Assisted Run-Time Metadata Management. - Jinli Rao; Tianyong Ao; Kui Dai; Xuecheng Zou (IEEE Comput. Archit. Lett., 2019)

A Chip-PCB Hybrid SC PUF Used for Anti-Desoldering and Depackaging-Attack Protection. - Meilin Wan; Zhen Zhang 047; Yin Zhang; Zhangqing He; Haoshuang Gu; Kui Dai; Xuecheng Zou (IEEE J. Solid State Circuits, 2024)

DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA. - Kui Dai; Zheren Xie; Shuanglong Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)