A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery. - Tae-Young Oh; Seung-Hyun Yi; Sung-Hyun Yang; Byong-Chan Lim; Kuk-Tae Hong (CICC, 2006)

A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS. - Young-Deuk Jeon; Young-Kyun Cho; Jae-Won Nam; Kwi-Dong Kim; Woo-Yol Lee; Kuk-Tae Hong; Jong-Kee Kwon (CICC, 2010)