Generalized Delay Optimization of Resistive Interconnections through an Extension of Logical Effort. - Kumar Venkat (ISCAS, 1993)

A structured design for test methodology. - Kumar Venkat (VTS, 1993)

Timing verification of dynamic circuits. - Kumar Venkat; Liang Chen; Ichiang Lin; Piyush Mistry; Pravin Madhani (IEEE J. Solid State Circuits, 1996)