Low Noise Low Power CMOS Telescopic-OTA for Bio-Medical Applications. - Bellamkonda Saidulu; Arun Manoharan; Kumaravel Sundaram 001 (Comput., 2016)

A high linearity and high gain Folded Cascode LNA for narrowband receiver applications. - S. Kumaravel 001; Anand Kukde; B. Venkataramani; R. Raja (Microelectron. J., 2016)

A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications. - M. Priyadharshni; Sundaram Kumaravel 001 (VDAT, 2018)

Modified recycling folded cascode OTA with enhancement in transconductanceand output impedance. - Sudheer Raja Venishetty; Kumaravel Sundaram 001 (Turkish J. Electr. Eng. Comput. Sci., 2019)

Power-efficient implementation of pseudo-random number generator using quantum dot cellular automata-based D Flip Flop. - S. Senthilnathan; S. Kumaravel 001 (Comput. Electr. Eng., 2020)

Low power and area efficient error tolerant adder for image processing application. - M. Priyadharshni; Sundaram Kumaravel 001 (Int. J. Circuit Theory Appl., 2020)

A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology. - Sabavat Satheesh Kumar; Kumaravel Sundaram 001; Sanjeevikumar Padmanaban; Jens Bo Holm-Nielsen; Frede Blaabjerg (IET Circuits Devices Syst., 2021)

An error efficient and low complexity approximate multi-bit adder for image processing applications. - M. Priyadharshni; Antra Raj Gupta; Venkatachalam Nithish Kumar; Sundaram Kumaravel 001 (Int. J. Circuit Theory Appl., 2021)

Blind Zone-Less Phase Frequency Detector for a Low-Power Phase-Locked Loop Architecture. - Marichamy Divya; Kumaravel Sundaram 001 (Circuits Syst. Signal Process., 2023)

Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications. - Marichamy Divya; Siva Kumar Rapina; S. Kumaravel 001 (VLSID, 2024)

High-k Metal-Insulator-Metal Capacitors for RF and Mixed-Signal VLSI Circuits: Challenges and Opportunities. - D. Kannadassan; K. Sivasankaran; S. Kumaravel 001; Chun-Hu Cheng; Maryam Shojaei Baghini; P. S. Mallick (Proc. IEEE, 2024)

Design of High-Performance Radix-Power-of-2 Butterfly Architectures for FFT Implementation by Cosine Coefficients Extraction. - Vijay Moni varghese; Kumaravel Sundaram 001 (Int. J. Circuit Theory Appl., 2025)