On Adaptive Fault Diagnosis for Multiprocessor Systems. - Kumiko Nomura; Toshinori Yamada; Shuichi Ueno (ISAAC, 2001)

Optimal adaptive parallel diagnosis for arrays. - Toshinori Yamada; Kumiko Nomura; Shuichi Ueno (ISCAS (3), 2003)

Sparse networks tolerating random faults. - Toshinori Yamada; Kumiko Nomura; Shuichi Ueno (Discret. Appl. Math., 2004)

On the Orthogonal Drawing of Outerplanar Graphs. - Kumiko Nomura; Satoshi Tayu; Shuichi Ueno (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

3D on-chip networking technology based on post-silicon devices for future networks-on-chip. - Shinobu Fujita; Kumiko Nomura; Keiko Abe; Thomas H. Lee (Nano-Net, 2006)

Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. - Kumiko Nomura; Keiko Abe; Shinobu Fujita; André DeHon (Nano-Net, 2006)

3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture. - Shinobu Fujita; Kumiko Nomura; Keiko Abe; Thomas H. Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

On the three-dimensional orthogonal drawing of series-parallel graphs (extended abstract). - Satoshi Tayu; Kumiko Nomura; Shuichi Ueno (ISCAS, 2008)

Perspectives and Issues in 3D-IC from Designers' Point of View. - Shinobu Fujita; Keiko Abe; Kumiko Nomura; Shinichi Yasuda; Tetsufumi Tanamoto (ISCAS, 2009)

On the two-dimensional orthogonal drawing of series-parallel graphs. - Satoshi Tayu; Kumiko Nomura; Shuichi Ueno (Discret. Appl. Math., 2009)

Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies. - Kumiko Nomura; Keiko Abe; Shinobu Fujita; Yasuhiko Kurosawa; Atsushi Kageshima (ISCAS, 2010)

Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation. - Kazutaka Ikegami; Keiko Abe; Kumiko Nomura; Shinichi Yasuda; Masato Oda; Shinobu Fujita (IPDPS Workshops, 2012)

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. - Hiroki Noguchi; Kumiko Nomura; Keiko Abe; Shinobu Fujita; Eishi Arima; Kyundong Kim; Takashi Nakada; Shinobu Miwa; Hiroshi Nakamura (DATE, 2013)

Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". - Shinobu Fujita; Kumiko Nomura; Hiroki Noguchi; Susumu Takeda; Keiko Abe (ASP-DAC, 2014)

Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. - Shinobu Fujita; Hiroki Noguchi; Kazutaka Ikegami; Susumu Takeda; Kumiko Nomura; Keiko Abe (ISIC, 2014)

Novel memory hierarchy with e-STT-MRAM for near-future applications. - Shinobu Fujita; Hiroki Noguchi; Kazutaka Ikegami; Susumu Takeda; Kumiko Nomura; Keiko Abe (VLSI-DAT, 2017)

Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays. - Takao Marukame; Kumiko Nomura; Mari Matusmoto; Satoshi Takaya; Yoshifumi Nishi (ISCAS, 2018)

Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning. - Takao Marukame; Junichi Sugino; Toshimitsu Kitamura; Kazuo Ishikawa; Koji Takahashi; Yutaka Tamura; Radu Berdan; Kumiko Nomura; Yoshifumi Nishi (ISCAS, 2019)

Dynamic Firing on Static Analog/Digital Neuron Circuits with Resistive Synapses for Time-Series Neural Network. - Takao Marukame; Junichi Sugino; Toshimitsu Kitamura; Kazuo Ishikawa; Koji Takahashi; Yutaka Tamura; Kumiko Nomura; Koichi Mizushima; Yoshifumi Nishi (ISCAS, 2020)

Synchronized Stepwise Control of Firing and Learning Thresholds in a Spiking Randomly Connected Neural Network toward Hardware Implementation. - Kumiko Nomura; Yoshifumi Nishi (CoRR, 2024)