STARBIST: Scan Autocorrelated Random Pattern Generation. - Kun-Han Tsai; Sybille Hellebrand; Janusz Rajski; Malgorzata Marek-Sadowska (DAC, 1997)

Scan-Encoded Test Pattern Generation for BIST. - Kun-Han Tsai; Malgorzata Marek-Sadowska; Janusz Rajski (ITC, 1997)

Star test: the theory and its applications. - Kun-Han Tsai; Janusz Rajski; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Embedded Deterministic Test for Low-Cost Manufacturing Test. - Janusz Rajski; Jerzy Tyszer; Mark Kassab; Nilanjan Mukherjee 001; Rob Thompson; Kun-Han Tsai; Andre Hertwig; Nagesh Tamarapalli; Grzegorz Mrugalski; Geir Eide; Jun Qian (ITC, 2002)

Multiple Fault Diagnosis Using n-Detection Tests. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (ICCD, 2003)

Impact of Multiple-Detect Test Patterns on Product Quality. - Brady Benware; Chris Schuermyer; Sreenevasan Ranganathan; Robert Madge; Prabhu Krishnamurthy; Nagesh Tamarapalli; Kun-Han Tsai; Janusz Rajski (ITC, 2003)

An Efficient and Effective Methodology on the Multiple Fault Diagnosis. - Zhiyuan Wang; Kun-Han Tsai; Malgorzata Marek-Sadowska; Janusz Rajski (ITC, 2003)

Compactor Independent Direct Diagnosis. - Wu-Tung Cheng; Kun-Han Tsai; Yu Huang 005; Nagesh Tamarapalli; Janusz Rajski (Asian Test Symposium, 2004)

Diagnosis of Hold Time Defects. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (ICCD, 2004)

Realizing High Test Quality Goals with Smart Test Resource Usage. - Xinli Gu; Cyndee Wang; Abby Lee; Bill Eklow; Kun-Han Tsai; Jan Arild Tofte; Mark Kassab; Janusz Rajski (ITC, 2004)

Built-in constraint resolution. - Grady Giles; Joel Irby; Daniela Toneva; Kun-Han Tsai (ITC, 2005)

Compression mode diagnosis enables high volume monitoring diagnosis flow. - Andreas Leininger; Peter Muhmenthaler; Wu-Tung Cheng; Nagesh Tamarapalli; Wu Yang; Kun-Han Hans Tsai (ITC, 2005)

Delay-fault diagnosis using timing information. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

At-Speed Testing with Timing Exceptions and Constraints-Case Studies. - Dhiraj Goswami; Kun-Han Tsai; Mark Kassab; Takeo Kobayashi; Janusz Rajski; Bruce Swanson; Darryl Walters; Yasuo Sato; Toshiharu Asaka; Takashi Aikyo (ATS, 2006)

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. - Xijiang Lin; Kun-Han Tsai; Chen Wang 014; Mark Kassab; Janusz Rajski; Takeo Kobayashi; Randy Klingenberg; Yasuo Sato; Shuji Hamada; Takashi Aikyo (ATS, 2006)

Delay Fault Diagnosis for Non-Robust Test. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Zhiyuan Wang; Kun-Han Tsai; Janusz Rajski (ISQED, 2006)

Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (ITC, 2006)

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. - Nandu Tendolkar; Dawit Belete; Bill Schwarz; Bob Podnar; Akshay Gupta; Steve Karako; Wu-Tung Cheng; Alex Babin; Kun-Han Tsai; Nagesh Tamarapalli; Greg Aldrich (ITC, 2006)

Improved Handling of False and Multicycle Paths in ATPG. - Vlado Vorisek; Bruce Swanson; Kun-Han Tsai; Dhiraj Goswami (VTS, 2006)

Analysis and methodology for multiple-fault diagnosis. - Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Test Generation in the Presence of Timing Exceptions and Constraints. - Dhiraj Goswami; Kun-Han Tsai; Mark Kassab; Janusz Rajski (DAC, 2007)

Enhanced testing of clock faults. - Teresa L. McLaurin; Rich Slobodnik; Kun-Han Tsai; Ana Keim (ITC, 2007)

Enhancing Transition Fault Model for Delay Defect Diagnosis. - Wu-Tung Cheng; Brady Benware; Ruifeng Guo; Kun-Han Tsai; Takeo Kobayashi; Kazuyuki Maruo; Michinobu Nakao; Yoshiaki Fukui; Hideyuki Otake (ATS, 2008)

A Robust Automated Scan Pattern Mismatch Debugger. - Kun-Han Tsai; Ruifeng Guo; Wu-Tung Cheng (ATS, 2008)

Improving the Resolution of Single-Delay-Fault Diagnosis. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

At-Speed Scan Test Method for the Timing Optimization and Calibration. - Kun-Han Tsai; Ruifeng Guo; Wu-Tung Cheng (Asian Test Symposium, 2009)

Speed-Path Debug Using At-Speed Scan Test Patterns. - Ruifeng Guo; Wu-Tung Cheng; Kun-Han Tsai (ETS, 2009)

Timing-Aware Multiple-Delay-Fault Diagnosis. - Vishal J. Mehta; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Improved weight assignment for logic switching activity during at-speed test pattern generation. - Meng-Fan Wu; Hsin-Cheih Pan; Teng-Han Wang; Jiun-Lang Huang; Kun-Han Tsai; Wu-Tung Cheng (ASP-DAC, 2010)

Scan based speed-path debug for a microprocessor. - Jing Zeng; Ruifeng Guo; Wu-Tung Cheng; Michael Mateja; Jing Wang; Kun-Han Tsai; Ken Amstutz (ETS, 2010)

A Low Complexity Transmitter Architecture and Its Application to PAPR Reduction in SFBC MIMO-OFDM Systems. - Chih-Peng Li; Sen-Hung Wang; Kun-Han Tsai (ICC, 2010)

A scalable quantitative measure of IR-drop effects for scan pattern generation. - Meng-Fan Wu; Kun-Han Tsai; Wu-Tung Cheng; Hsin-Cheih Pan; Jiun-Lang Huang; Augusli Kifli (ICCAD, 2010)

Test cycle power optimization for scan-based designs. - Kun-Han Tsai; Yu Huang 005; Wu-Tung Cheng; Ting-Pu Tai; Augusli Kifli (ITC, 2010)

Programmable Leakage Test and Binning for TSVs. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (Asian Test Symposium, 2012)

Small delay testing for TSVs in 3-D ICs. - Shi-Yu Huang; Yu-Hsiang Lin; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter; Yung-Fa Chou; Ding-Ming Kwai (DAC, 2012)

A unified method for parametric fault characterization of post-bond TSVs. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter (ITC, 2012)

Mid-bond Interposer Wire Test. - Li-Ren Huang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter (Asian Test Symposium, 2013)

Multicycle-aware At-speed Test Methodology. - Kun-Han Tsai; Xijiang Lin (Asian Test Symposium, 2013)

At-speed BIST for interposer wires supporting on-the-spot diagnosis. - Shi-Yu Huang; Jeo-Yen Lee; Kun-Han Tsai; Wu-Tung Cheng (IOLTS, 2013)

Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. - Shi-Yu Huang; Li-Ren Huang; Kun-Han Tsai; Wu-Tung Cheng (ITC, 2013)

Design rule check on the clock gating logic for testability and beyond. - Kun-Han Tsai; Shuo Sheng (ITC, 2013)

Improve speed path identification with suspect path expressions. - Jiun-Lang Huang; Kun-Han Tsai; Yu-Ping Liu; Ruifeng Guo; Manish Sharma; Wu-Tung Cheng (VLSI-DAT, 2013)

Oscillation-Based Prebond TSV Test. - Li-Ren Huang; Shi-Yu Huang; Stephen K. Sunter; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control. - Shi-Yu Huang; Yu-Hsiang Lin; Li-Ren Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter; Yung-Fa Chou; Ding-Ming Kwai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs. - Shi-Yu Huang; Hua-Xuan Li; Zeng-Fu Zeng; Kun-Han Tsai; Wu-Tung Cheng (ATS, 2014)

Testability-Driven Fault Sampling for Deterministic Test Coverage Estimation of Large Designs. - Kun-Han Tsai (ATS, 2014)

On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. - Shi-Yu Huang; Zeng-Fu Zeng; Kun-Han Tsai; Wu-Tung Cheng (ETS, 2014)

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs. - Li-Ren Huang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Pulse-Vanishing Test for Interposers Wires in 2.5-D IC. - Shi-Yu Huang; Jeo-Yen Lee; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Kun-Han Hans Tsai; Wu-Tung Cheng (DATE, 2015)

Monitoring the delay of long interconnects via distributed TDC. - Meng-Ting Tsai; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (ITC, 2015)

A test-application-count based learning technique for test time reduction. - Guo-Yu Lin; Kun-Han Tsai; Jiun-Lang Huang; Wu-Tung Cheng (VLSI-DAT, 2015)

Clock-domain-aware test for improving pattern compression. - Kun-Han Tsai; Janusz Rajski (VLSI-DAT, 2015)

Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Hua-Xuan Li; Zeng-Fu Zeng; Kun-Han Hans Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Zeng-Fu Zeng; Kun-Han Hans Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Testing of small delay faults in a clock network. - Shaofu Yang; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (ETS, 2016)

A wide-range clock signal generation scheme for speed grading of a logic core. - Shi-Yu Huang; Tzu-Heng Huang; Kun-Han Tsai; Wu-Tung Cheng (HPCS, 2016)

Online slack-time binning for IO-registered die-to-die interconnects. - Chih-Chieh Zheng; Shi-Yu Huang; Shyue-Kung Lu; Ting-Chi Wang; Kun-Han Tsai; Wu-Tung Cheng (ITC, 2016)

Versatile Transition-Time Monitoring for Interconnects via Distributed TDC. - Shi-Yu Huang; Chih-Chieh Cheng; Meng-Ting Tsai; Kuan-Chen Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Des. Test, 2016)

Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects. - Shi-Yu Huang; Meng-Ting Tsai; Kun-Han Tsai; Wu-Tung Cheng (IEEE Des. Test, 2016)

Test Coverage Analysis for Designs with Timing Exceptions. - Kun-Han Tsai; Srinivasan Gopalakrishnan (ATS, 2017)

X-Sources Analysis for Improving the Test Quality. - Kun-Han Tsai (ITC-Asia, 2018)

Circuit and Methodology for Testing Small Delay Faults in the Clock Network. - Shaofu Yang; Zhi-Yuan Wen; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. - Mason Chern; Shih-Wei Lee; Shi-Yu Huang; Yu Huang 005; Gaurav Veda; Kun-Han Hans Tsai; Wu-Tung Cheng (ASP-DAC, 2019)

TEA: A Test Generation Algorithm for Designs with Timing Exceptions. - Naixing Wang; Chen Wang 014; Kun-Han Tsai; Wu-Tung Cheng; Xijiang Lin; Mark Kassab; Irith Pomeranz (ATS, 2019)

Race and Glitch Handling: A Test Perspective. - Kun-Han Tsai (ITC-Asia, 2019)

GPU-based Hybrid Parallel Logic Simulation for Scan Patterns. - Liyang Lai; Qiting Zhang; Kun-Han Hans Tsai; Wu-Tung Cheng (ITC-Asia, 2020)

Test Challenges of Intel IA Cores. - Uri Shpiro; Khen Wee; Kun-Han Tsai; Justyna Zawada; Xijiang Lin (ITC, 2020)

Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. - Mason Chern; Shih-Wei Lee; Shi-Yu Huang; Yu Huang 005; Gaurav Veda; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

GPGPU-Based ATPG System: Myth or Reality? - Liyang Lai; Kun-Han Tsai; Huawei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Timing Critical Path Validation for Intel ATOM Cores Using Structural Test. - Wei Li; Shih-Yu Yang; Khen Wee; Ricardo Sanchez; Jay Desai; Kun-Han Tsai; Xijiang Lin (VTS, 2021)

Timing-Verification Test Generation Targeting Small Delay Defects. - Jiezhong Wu; Nilanjan Mukherjee 001; Irith Pomeranz; Kun-Han Tsai; Janusz Rajski (VTS, 2025)