Fail Pattern Identification for Memory Built-In Self-Repair. - Rei-Fu Huang; Chin-Lung Su; Cheng-Wen Wu; Shen-Tien Lin; Kun-Lun Luo; Yeong-Jar Chang (Asian Test Symposium, 2004)

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen; Ji-Jan Chen; Kun-Lun Luo; Wen Ching Wu (ITC, 2006)

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. - Shih-Ping Lin 001; Chung-Len Lee 001; Jwu-E Chen; Ji-Jan Chen; Kun-Lun Luo; Wen Ching Wu (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories. - Chin-Lung Su; Rei-Fu Huang; Cheng-Wen Wu; Kun-Lun Luo; Wen Ching Wu (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. - Bing-Chuan Bai; Chun-Lung Hsu; Ming-Hsueh Wu; Chen-An Chen; Yee-Wen Chen; Kun-Lun Luo; Liang-Chia Cheng; James Chien-Mo Li (Asian Test Symposium, 2013)

Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs. - Chen-An Chen; Yee-Wen Chen; Chun-Lung Hsu; Ming-Hsueh Wu; Kun-Lun Luo; Bing-Chuan Bai; Liang-Chia Cheng (Asian Test Symposium, 2013)

Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM. - Kun-Lun Luo; Ming-Hsueh Wu; Chun-Lung Hsu; Chen-An Chen (J. Electron. Test., 2016)