Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. - Kaiyan Chang; Kun Wang 055; Nan Yang; Ying Wang 001; Dantong Jin; Wenlong Zhu; Zhirong Chen; Cangyuan Li; Hao Yan; Yunhao Zhou; Zhuoliang Zhao; Yuan Cheng; et al. (DAC, 2024)

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. - Kaiyan Chang; Zhirong Chen; Yunhao Zhou; Wenlong Zhu; Kun Wang 055; Haobo Xu; Cangyuan Li; Mengdi Wang; Shengwen Liang; Huawei Li 001; Yinhe Han 001; Ying Wang 001 (ICCAD, 2024)

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. - Kun Wang 055; Kaiyan Chang; Mengdi Wang; Xingqi Zou; Haobo Xu; Yinhe Han 001; Ying Wang 001 (ASP-DAC, 2025)

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. - Kun Wang 055; Kaiyan Chang; Mengdi Wang; Xinqi Zou; Haobo Xu; Yinhe Han 001; Ying Wang 001 (CoRR, 2025)