Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. - Kun Young Chung; Sandeep K. Gupta 001 (ITC, 2003)

Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. - Kun Young Chung; Sandeep K. Gupta 001 (VTS, 2006)

Efficient Scheduling of Path Delay Tests for Latch-Based Circuits. - Kun Young Chung; Sandeep K. Gupta 001 (VTS, 2009)

Design and test of latch-based circuits to maximize performance, yield, and delay test quality. - Kun Young Chung; Sandeep K. Gupta 001 (ITC, 2010)

Innovative practices session 6C: Latest practices in test compression. - Jonathon E. Colburn; Kun Young Chung; Haluk Konuk; Y. Dong (VTS, 2013)

Test Compression Improvement with EDT Channel Sharing in SoC Designs. - Yu Huang 005; Mark Kassab; Jay Jahangiri; Janusz Rajski; Wu-Tung Cheng; Dongkwan Han; Jihye Kim 002; Kun Young Chung (NATW, 2014)

Learning-based prediction of embedded memory timing failures during initial floorplan design. - Wei-Ting Jonas Chan; Kun Young Chung; Andrew B. Kahng; Nancy D. MacDonald; Siddhartha Nath (ASP-DAC, 2016)

Comprehensive optimization of scan chain timing during late-stage IC implementation. - Kun Young Chung; Andrew B. Kahng; Jiajia Li 002 (DAC, 2016)

Innovative practices session 9C DFT and data for diagnostics. - Kun Young Chung; Stefano Di Carlo (VTS, 2017)

Industry Evaluation of Reversible Scan Chain Diagnosis. - Soumya Mittal; Szczepan Urban; Kun Young Chung; Jakub Janicki; Wu-Tung Cheng; Martin Parley; Manish Sharma; Shaun Nicholson (ITC, 2022)