RESTA: a robust and extendable symbolic timing analysis tool. - Kundan Nepal; Hui-Yuan Song; R. Iris Bahar; Joel Grodstein (ACM Great Lakes Symposium on VLSI, 2004)

Design evolution of the Trinity College IGVC robot ALVIN. - Michelle Bovard; Matthew Gillette; Trishan R. de Lanerolle; Bozidar Marinkovic; Nhon H. Trinh; Peter Votto; David J. Ahlgren; Kundan Nepal; Amir Tamrakar (J. Field Robotics, 2004)

Designing logic circuits for probabilistic computation in the presence of noise. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (DAC, 2005)

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. - R. Iris Bahar; Hui-Yuan Song; Kundan Nepal; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Designing MRF based error correcting circuits for memory elements. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (DATE, 2006)

Optimizing noise-immune nanoscale circuits using principles of Markov random fields. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (ACM Great Lakes Symposium on VLSI, 2006)

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (IEEE Micro, 2006)

Timing analysis for full-custom circuits using symbolic DC formulations. - Hui-Yuan Song; Kundan Nepal; R. Iris Bahar; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (DATE, 2007)

Designing Nanoscale Logic Circuits Based on Markov Random Fields. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (J. Electron. Test., 2007)

Using Implications for Online Error Detection. - Kundan Nepal; Nuno Alves; Jennifer Dworak; R. Iris Bahar (ITC, 2008)

Detecting errors using multi-cycle invariance information. - Nuno Alves; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (DATE, 2009)

Compacting test vector sets via strategic use of implications. - Nuno Alves; Jennifer Dworak; R. Iris Bahar; Kundan Nepal (ICCAD, 2009)

Improving the testability and reliability of sequential circuits with invariant logic. - Nuno Alves; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (ACM Great Lakes Symposium on VLSI, 2010)

A Cost Effective Approach for Online Error Detection Using Invariant Relationships. - Nuno Alves; Alison Buben; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. - Nuno Alves; Yiwen Shi; Nicholas Imbriglia; Jennifer Dworak; Kundan Nepal; R. Iris Bahar (ETS, 2011)

Wow! linear systems and signal processing is fun! - Maurice F. Aburdene; Kundan Nepal (FIE, 2011)

Enhancing online error detection through area-efficient multi-site implications. - Nuno Alves; Yiwen Shi; Jennifer Dworak; R. Iris Bahar; Kundan Nepal (VTS, 2011)

Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults. - Carson Dunbar; Kundan Nepal (J. Comput., 2011)

Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors. - Kundan Nepal (NEWCAS, 2012)

Using implications to choose tests through suspect fault identification. - Jennifer Dworak; Kundan Nepal; Nuno Alves; Yiwen Shi; Nicholas Imbriglia; R. Iris Bahar (ACM Trans. Design Autom. Electr. Syst., 2012)

Built-in Self-Repair in a 3D die stack using programmable logic. - Kundan Nepal; Xi Shen; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (DFTS, 2013)

Repairing a 3-D Die-Stack Using Available Programmable Logic. - Kundan Nepal; Soha Alhelaly; Jennifer Dworak; R. Iris Bahar; Theodore W. Manikas; Ping Guikundan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Using Existing Reconfigurable Logic in 3D Die Stacks for Test. - Fanchen Zhang; Yi Sun; Xi Shen; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; Ping Gui; R. Iris Bahar; Al Crouch; John C. Potter (NATW, 2016)

Stimulating curiosity and the ability to formulate technical questions in an electric circuits course using the question formulation technique (QFT). - Heath J. LeBlanc; Kundan Nepal; Greg S. Mowry (FIE, 2017)

Combinational hardware Trojan detection using logic implications. - Noah Cornell; Kundan Nepal (MWSCAS, 2017)

Detecting a trojan die in 3D stacked integrated circuits. - Soha Alhelaly; Jennifer Dworak; Theodore W. Manikas; Ping Gui; Kundan Nepal; Alfred L. Crouch (NATW, 2017)

Tools for the 3Cs of Entrepreneurially Minded Learning (EML). - Heath J. LeBlanc; Kundan Nepal; Greg S. Mowry; Alan Cheville (FIE, 2018)

Low cost Brussels sprouts harvester for small farms. - Milad Audi; William Frost; Jose Henriquez; Nathan Jones; Janssen Hang; Kundan Nepal (GHTC, 2019)

Low-cost instrumentation of high-tunnels for a small co-op farm. - Jeremy Ziemer; Austin Stokes; Janssen Hang; Kundan Nepal (GHTC, 2019)

Test Architecture for Fine Grained Capture Power Reduction. - Yi Sun; Hui Jiang; Lakshmi Ramakrishnan; Matan Segal; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (ICECS, 2019)

Dilated Temporal Convolutional Neural Network Architecture with Independent Component Layer for Human Activity Recognition. - Matthew Ward; Cheol-Hong Min; Hassan A. Salamy; Kundan Nepal (ICECS, 2019)

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. - Yi Sun; Fanchen Zhang; Hui Jiang; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (J. Electron. Test., 2019)

True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors. - Daniel Hellkamp; Kundan Nepal (J. Circuits Syst. Comput., 2019)

Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications. - Dulana Rupanetti; Kundan Nepal; Hassan A. Salamy; Cheol-Hong Min (CCWC, 2020)

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. - Yi Sun; Hui Jiang; Lakshmi Ramakrishnan; Jennifer Dworak; Kundan Nepal; Theodore W. Manikas; R. Iris Bahar (ITC, 2021)

3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations. - Soha Alhelaly; Jennifer Dworak; Kundan Nepal; Theodore W. Manikas; Ping Gui; Alfred L. Crouch (IEEE Trans. Emerg. Top. Comput., 2021)

Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis. - Dulana Rupanetti; Hassan A. Salamy; Cheol-Hong Min; Kundan Nepal (Int. J. Parallel Emergent Distributed Syst., 2022)

Harvesting Wasted Clock Cycles for Efficient Online Testing. - Eslam Yassien; Yongjia Xu; Hui Jiang; Thach Nguyen; Jennifer Dworak; Theodore W. Manikas; Kundan Nepal (ETS, 2023)

Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift. - Hui Jiang; Fanchen Zhang; Jennifer Dworak; Kundan Nepal; Theodore W. Manikas (J. Electron. Test., 2023)

Dual Use Circuitry for Early Failure Warning and Test. - Alexander Coyle; Hui Jiang; Jennifer Dworak; Theodore W. Manikas; Kundan Nepal (ISQED, 2024)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)