A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM. - Toshio Takeshima; Masahide Takada; Hiroki Koike; Hiroshi Watanabe; Shigeru Koshimaru; Kenjiro Mitake; Wataru Kikuchi; Takaho Tanigawa; Tatsunori Murotani; Kenji Noda; Kazuhiro Tasaka; Koji Yamanaka; et al. (IEEE J. Solid State Circuits, 1990)

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. - Akira Tanabe; Toshio Takeshima; Hiroki Koike; Yoshiharu Aimoto; Masahide Takada; Toshiyuki Ishijima; Naoki Kasai; Hiromitsu Hada; Kentaro Shibahara; Takemitsu Kunio; Takaho Tanigawa; Takanori Saeki; et al. (IEEE J. Solid State Circuits, 1992)

A 1-Gb DRAM for file applications. - Tadahiko Sugibayashi; Isao Naritake; Satoshi Utsugi; Kentaro Shibahara; Ryuichi Oikawa; Hidemitsu Mori; Shouichi Iwao; Tatsunori Murotani; Kuniaki Koyama; Shinichi Fukuzawa; Toshiro Itani; Kunihiko Kasama; et al. (IEEE J. Solid State Circuits, 1995)

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay. - Takanori Saeki; Yuji Nakaoka; Mamoru Fujita; Akihito Tanaka; Kyoichi Nagata; Kenichi Sakakibara; Tatsuya Matano; Yukio Hoshino; Kazutaka Miyano; Satoshi Isa; Shigeyuki Nakazawa; Eiichiro Kakehashi; et al. (IEEE J. Solid State Circuits, 1996)

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme. - Yasuhiro Takai; Mamoru Fujita; Kyoichi Nagata; Satoshi Isa; Shigeyuki Nakazawa; Atsunori Hirobe; Hiroaki Ohkubo; Masato Sakao; Shinichi Horiba; Tadashi Fukase; Yoshihiro Takaishi; Makoto Matsuo; et al. (IEEE J. Solid State Circuits, 2000)

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. - Tatsuya Matano; Yasuhiro Takai; Tsugio Takahashi; Yuusuke Sakito; Isamu Fujii; Yoshihiro Takaishi; Hiroki Fujisawa; Shuichi Kubouchi; Seiji Narui; Koji Arai; Makoto Morino; Masayuki Nakamura; et al. (IEEE J. Solid State Circuits, 2003)