High density 3D integration by pre-applied Inter Chip Fill. - Akihiro Horibe; Kuniaki Sueoka; Katsuyuki Sakuma; Sayuri Kohara; Keiji Matsumoto; Hidekazu Kikuchi; Yasumitsu Orii; Toshiro Mitsuhashi; Fumiaki Yamada (3DIC, 2010)

Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration. - Sayuri Kohara; Akihiro Horibe; Kuniaki Sueoka; Keiji Matsumoto; Fumiaki Yamada; Yasumitsu Orii; Katsuyuki Sakuma; Takahiro Kinoshita; Takashi Kawakami (3DIC, 2011)

Thermo-mechanical evaluation of 3D packages. - Sayuri Kohara; Akihiro Horibe; Kuniaki Sueoka; Keiji Matsumoto; Fumiaki Yamada; Hiroyuki Mori; Yasumitsu Orii (3DIC, 2013)

Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack. - Keiji Matsumoto; Soichiro Ibaraki; Kuniaki Sueoka; Katsuyuki Sakuma; Hidekazu Kikuchi; Hiroyuki Mori; Yasumitsu Orii; Fumiaki Yamada; Kohei Fujihara; Junichi Takamatsu; Koji Kondo (3DIC, 2013)

Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration. - Kuniaki Sueoka; Akihiro Horibe; T. Aoki; Sayuri Kohara; Kazushige Toriyama; Hiroyuki Mori; Yasumitsu Orii (3DIC, 2015)