Dynamically Adaptable CMOS Winner-Take-All Neural Network. - Kunihiko Iizuka; Masayuki Miyamoto; Hirofumi Matsui (NIPS, 1996)

A parallel analog intelligent vision sensor with a variable receptive field. - Tetsuya Yagi; Seiji Kameda; Kunihiko Iizuka (Syst. Comput. Jpn., 1999)

A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator. - Yoshihisa Fujimoto; Shuichi Kawama; Kunihiko Iizuka; Masayuki Miyamoto; Daniel Senderowicz (CICC, 2000)

Embedded anti-aliasing in switched-capacitor ladder filters. - Daniel Senderowicz; Shin'ichiro Azuma; Shuichi Kawama; Kunihiko Iizuka; Masayuki Miyamoto (CICC, 2001)

CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops. - Kunihiko Iizuka; Masayuki Miyamoto; Yoshiji Ohta; Takahiro Suyama; Keita Hara; Shuichi Kawama; Hirofumi Matsui; Shin'ichiro Azuma; Shigenari Taguchi; Yoshihisa Fujimoto; Daniel Senderowicz (IEEE J. Solid State Circuits, 2001)

Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation. - Shin'ichiro Azuma; Shuichi Kawama; Kunihiko Iizuka; Masayuki Miyamoto; Daniel Senderowicz (IEEE J. Solid State Circuits, 2002)

A high OIP3 quadrature mixer using cross-coupled transconductor. - Masato Koutani; Kunihiko Iizuka (CICC, 2005)

Fast Automatic Tuning of Channel Selection Filters Based on Phase Delay Calibration. - Koutani Kagoshima; Shuichi Kawama; Shinji Toyoyama; Kunihiko Iizuka (CICC, 2006)

A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration. - Mutsuo Daito; Hirofumi Matsui; Masaya Ueda; Kunihiko Iizuka (IEEE J. Solid State Circuits, 2006)

A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s. - Kunihiko Iizuka; Hirofumi Matsui; Masaya Ueda; Mutsuo Daito (IEEE J. Solid State Circuits, 2006)

A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications. - Takae Sakai; Shinya Ito; Nobuyoshi Kaiki; Atsushi Sakai; Mamoru Okazaki; Masayuki Natsumi; Akira Saito; Kazumasa Kioi; Masato Koutani; Koutani Kagoshima; Shuichi Kawama; Hiroshi Kijima; et al. (ISSCC, 2007)

A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor. - Kunihiko Iizuka; Hiroshi Kawamura; Takanobu Fujiwara; Kanetomo Kagoshima; Shuichi Kawama; Hiroshi Kijima; Masato Koutani; Shinji Toyoyama; Keiichi Sakuno (IEEE J. Solid State Circuits, 2007)

A Digitally Controlled Variable-Gain Low-Noise Amplifier With Strong Immunity to Interferers. - Masato Koutani; Hiroshi Kawamura; Shinji Toyoyama; Kunihiko Iizuka (IEEE J. Solid State Circuits, 2007)

RF Variable-Gain Amplifiers and AGC Loops for Digital TV Receivers. - Kunihiko Iizuka; Masato Koutani; Takeshi Mitsunaka; Hiroshi Kawamura; Shinji Toyoyama; Masayuki Miyamoto; Akira Matsuzawa (IEICE Trans. Electron., 2008)

A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS. - Yoshihisa Fujimoto; Yusuke Kanazawa; Pascal Lo Ré; Kunihiko Iizuka (IEEE J. Solid State Circuits, 2009)

Foreword. - Kunihiko Iizuka (IEICE Trans. Electron., 2010)

Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing. - Mutsuo Daito; Yoshiro Nakata; Satoshi Sasaki; Hiroyuki Gomyo; Hideki Kusamitsu; Yoshio Komoto; Kunihiko Iizuka; Katsuyuki Ikeuchi; Gil-Su Kim; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2011)

9dB NF and +11dBm OIP3 CMOS Single Conversion Front-End for a Satellite Low-Noise Block Down-Converter. - Takeshi Mitsunaka; Yusuke Kishino; Masafumi Yamanoue; Kunihiko Iizuka; Minoru Fujishima (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

8-GHz Locking Range and 0.4-pJ Low-Energy Differential Dual-Modulus 10/11 Prescaler. - Takeshi Mitsunaka; Masafumi Yamanoue; Kunihiko Iizuka; Minoru Fujishima (IEICE Trans. Electron., 2014)

A 24-bit multi-functional sensor analog front end employing low noise biasing technique with 8.2nV/√Hz input referred noise. - Masahiko Maruyama; Shigenari Taguchi; Masafumi Yamanoue; Kunihiko Iizuka (A-SSCC, 2015)

97-mW 8-Phase CMOS VCO and Dividers for a 134-GHz PLL Synthesizer. - Takeshi Mitsunaka; Kunihiko Iizuka; Minoru Fujishima (IEICE Trans. Electron., 2015)

28.3 CMOS biosensor IC focusing on dielectric relaxations of biological water with 120GHz and 60GHz oscillator arrays. - Takeshi Mitsunaka; Nobuyuki Ashida; Akira Saito; Kunihiko Iizuka; Tetsuhito Suzuki; Yuichi Ogawa; Minoru Fujishima (ISSCC, 2016)

An Analog Front-End for a Multifunction Sensor Employing a Weak-Inversion Biasing Technique With 26 nVrms, 25 aCrms, and 19 fArms Input-Referred Noise. - Masahiko Maruyama; Shigenari Taguchi; Masafumi Yamanoue; Kunihiko Iizuka (IEEE J. Solid State Circuits, 2016)

CMOS Biosensor IC Focusing on Dielectric Relaxations of Biological Water With 120 and 60 GHz Oscillator Arrays. - Takeshi Mitsunaka; Daiki Sato; Nobuyuki Ashida; Akira Saito; Kunihiko Iizuka; Tetsuhito Suzuki; Yuichi Ogawa; Minoru Fujishima (IEEE J. Solid State Circuits, 2016)