Evaluation of delay-time degradation of low-voltage BiCMOS based on a novel analytical delay-time modeling. - Minoru Fujishima; Kunihiro Asada; Takuo Sugano (IEEE J. Solid State Circuits, 1991)

A general and efficient mask pattern generator for non-series-parallel CMOS transistor network. - H. Zhang; Kunihiro Asada (Synthesis for Control Dominated Circuits, 1992)

Low-power 1/2 frequency dividers using 0.1- mu m CMOS circuits built with ultrathin SIMOX substrates. - Minoru Fujishima; Kunihiro Asada; Yasuhisa Omura; Katsutoshi Izumi (IEEE J. Solid State Circuits, 1993)

A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs. - Makoto Ikeda; Kunihiro Asada (EDAC-ETC-EUROASIC, 1994)

Design Methodology for Low Power Data Compressors Based on a Window Detector in a 54X54 Bit Multiplier. - Minkyu Song; Kunihiro Asada (ISCAS, 1995)

Crosstalk noise in high density and high speed interconnections due to inductive coupling. - Tetsuhisa Mido; Kunihiro Asada (ASP-DAC, 1997)

Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. - Satoshi Komatsu; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 1998)

An Analysis on VLSI Interconnection Considering Skin Effect. - Tetsuhisa Mido; Kunihiro Asada (ASP-DAC, 1998)

One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects. - Rimon Ikeno; Hiroshi Ito; Kunihiro Asada (VLSI Design, 1998)

Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. - Satoshi Komatsu; Makoto Ikeda; Kunihiro Asada (Great Lakes Symposium on VLSI, 1999)

Standard design flows of Logic LSIs in Japanese universities and VDEC. - Makoto Ikeda; Kunihiro Asada (MSE, 1999)

A binary image sensor with flexible motion vector detection using block matching method. - Tomohiro Nezuka; Takafumi Fujita; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2000)

Optimum Functional Decomposition for LUT-Based FPGA Synthesis. - Jian Qiao; Makoto Ikeda; Kunihiro Asada (FPL, 2000)

DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path. - Makoto Ikeda; Hideyuki Aoki; Kunihiro Asada (ISQED, 2000)

A Binary Image Sensor for Motion Detection. - Tomohiro Nezuka; Takafumi Fujita; Makoto Ikeda; Kunihiro Asada (J. Robotics Mechatronics, 2000)

A system level memory power optimization technique using multiple supply and threshold voltages. - Tohru Ishihara; Kunihiro Asada (ASP-DAC, 2001)

A smart position sensor for 3-D measurement. - Tomohiro Nezuka; Masashi Hoshino; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2001)

Finding an optimal functional decomposition for LUT-based FPGA synthesis. - Jian Qiao; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2001)

A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. - Hiroaki Yamaoka; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2001)

Computational Cost Reduction in Extracting Inductance. - Yusuke Nakashima; Makoto Ikeda; Kunihiro Asada (ISQED, 2001)

Quick power supply noise estimation using hierarchically derived transfer functions. - Satoshi Sugiyama; Makoto Ikeda; Kunihiro Asada (ICECS, 2002)

Logic synthesis for PLA with 2-input logic elements. - Hiroaki Yoshida; Hiroaki Yamaoka; Makoto Ikeda; Kunihiro Asada (ISCAS (3), 2002)

An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. - Tohru Ishihara; Kunihiro Asada (ASP-DAC/VLSI Design, 2002)

Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. - Hiroaki Yoshida; Hiroaki Yamaoka; Makoto Ikeda; Kunihiro Asada (ASP-DAC/VLSI Design, 2002)

Theoretical study of stubs for power line noise reduction [LSI applications]. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (CICC, 2003)

A high-speed and low-voltage associative co-processor with Hamming distance ordering using word-parallel and hierarchical search architecture. - Yusuke Oike; Makoto Ikeda; Kunihiro Asada (CICC, 2003)

A smart image sensor with high-speed feeble ID-beacon detection for augmented reality system. - Yusuke Oike; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2003)

A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design. - Hiroaki Yamaoka; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2003)

High-speed position detector using new row-parallel architecture for fast collision prevention system. - Yusuke Oike; Makoto Ikeda; Kunihiro Asada (ISCAS (4), 2003)

Comparative Study On Verilog-Based And C-Based Hardware Design Education. - Tohru Ishihara; Satoshi Komatsu; Makoto Ikeda; Masahiro Fujita; Kunihiro Asada (MSE, 2003)

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2004)

Design of real-time VGA 3-D image sensor using mixed-signal techniques. - Yusuke Oike; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2004)

A word-parallel digital associative engine with wide search range based on Manhattan distance. - Yusuke Oike; Makoto Ikeda; Kunihiro Asada (CICC, 2004)

Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime. - Mohamed Abbas; Makoto Ikeda; Kunihiro Asada (DFT, 2004)

Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ISQED, 2004)

Smart Access Image Sensors for High-Speed and High-Resolution 3-D Measurement based on Light-Section Method. - Yusuke Oike; Makoto Ikeda; Kunihiro Asada (Intell. Autom. Soft Comput., 2004)

A 120×110 position sensor with the capability of sensitive and selective light detection in wide dynamic range for robust active range finding. - Yusuke Oike; Makoto Ikeda; Kunihiro Asada (IEEE J. Solid State Circuits, 2004)

A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture. - Yusuke Oike; Makoto Ikeda; Kunihiro Asada (IEEE J. Solid State Circuits, 2004)

Design and implementation of real-time 3-D image sensor with 640 × 480 pixel resolution. - Yusuke Oike; Makoto Ikeda; Kunihiro Asada (IEEE J. Solid State Circuits, 2004)

Analysis of low noise three-phase asynchronous data transmission. - Nan Li; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2005)

Autonomous di/dt noise control scheme for margin aware operation. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2005)

Exact minimum-width transistor placement without dual constraint for CMOS cells. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ACM Great Lakes Symposium on VLSI, 2005)

On-chip non-periodic high-swing noise detector. - Mohamed Abbas; Makoto Ikeda; Kunihiro Asada (ICECS, 2005)

An algebraic approach for transistor circuit synthesis. - Hiroaki Yoshida; Makoto Ikeda; Kunihiro Asada (ICECS, 2005)

Real-time 3-D measurement system based on light-section method using smart image sensor. - Yusuke Yachide; Yusuke Oike; Makoto Ikeda; Kunihiro Asada (ICIP (3), 2005)

A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells. - Ulkuhan Ekinciel; Hiroaki Yamaoka; Hiroaki Yoshida; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Inf. Syst., 2005)

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Stub vs. Capacitor for Power Supply Noise Reduction. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2005)

On-chip di/dt Detector Circuit. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2005)

Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2005)

A 375 × 365 high-speed 3-D range-finding image sensor using row-parallel search architecture and multisampling technique. - Yusuke Oike; Makoto Ikeda; Kunihiro Asada (IEEE J. Solid State Circuits, 2005)

On-chip 8GHz non-periodic high-swing noise detector. - Mohamed Abbas; Makoto Ikeda; Kunihiro Asada (DATE, 2006)

Timing-driven cell layout de-compaction for yield optimization by critical area minimization. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (DATE, 2006)

Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow. - Mohamed Abbas; Makoto Ikeda; Kunihiro Asada (DDECS, 2006)

Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ICECS, 2006)

Pre-conditioning Free Footless DCVSL for High-performance Datapaths. - Makoto Ikeda; Kin Hooi Dia; Kunihiro Asada (ICECS, 2006)

Tamper Resistivity Analysis for Nano-meter LSI with Process Variations. - Makoto Ikeda; Hiroshi Yamauchi; Kunihiro Asada (ICECS, 2006)

4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS. - Masahiro Sasaki; Makoto Ikeda; Kunihiro Asada (ICECS, 2006)

High-Speed 3-D Measurement System Using Smart Image Sensor and FPGA Based 3-D Engine. - Yusuke Yachide; Makoto Ikeda; Kunihiro Asada (ICECS, 2006)

Exact Minimum Logic Factoring via Quantified Boolean Satisfiability. - Hiroaki Yoshida; Makoto Ikeda; Kunihiro Asada (ICECS, 2006)

Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ISCAS, 2006)

On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function. - Mohamed Abbas; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2006)

Noise Immunity Investigation of Low Power Design Schemes. - Mohamed Abbas; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2006)

LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil. - Taisuke Kazama; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2006)

Autonomous di/dt Control of Power Supply for Margin Aware Operation. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2006)

A Structural Approach for Transistor Circuit Synthesis. - Hiroaki Yoshida; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. - Taisuke Kazama; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2007)

Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology. - Zhicheng Liang; Makoto Ikeda; Kunihiro Asada (DDECS, 2007)

FPGA-Based 3-D engine for high-speed 3-D measurement based on light-section method. - Yusuke Yachide; Makoto Ikeda; Kunihiro Asada (FPT, 2007)

Datapath Delay Distributions for Data/Instruction against PVT Variations in 90nm CMOS. - Makoto Ikeda; Ken Ishii; Taku Sogabe; Kunihiro Asada (ICECS, 2007)

Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-meter CMOS. - Kenichiro Kurihara; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ICECS, 2007)

3.5-Gb/s extended frequency range wave-pipeline PRBS Generator in 0.18-μm CMOS. - Masahiro Sasaki; Makoto Ikeda; Kunihiro Asada (ICECS, 2007)

OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ISQED, 2007)

LAGS System Using Data/Instruction Grain Power Control. - Makoto Ikeda; Taku Sogabe; Ken Ishii; Masayuki Mizuno; Toru Nakura; Koichi Nose; Kunihiro Asada (ISSCC, 2007)

VLSI CAD Education and Exercise Course with Public Domain Tools. - Satoshi Komatsu; Kazuyoshi Takagi; Masahiro Fujita; Kunihiro Asada (MSE, 2007)

Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Circuit design using stripe-shaped PMELA TFTs on glass. - Keita Ikai; Jinmyoung Kim; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2009)

Measurement of power supply noise tolerance of self-timed processor. - Kunihiro Asada; Taku Sogabe; Toru Nakura; Makoto Ikeda (DDECS, 2009)

All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. - Sanad Bushnaq; Toru Nakura; Makoto Ikeda; Kunihiro Asada (DDECS, 2009)

SAT-based ATPG testing of inter- and intra-gate bridging faults. - Toru Nakura; Yutaro Tatemura; Görschwin Fey; Makoto Ikeda; Satoshi Komatsu; Kunihiro Asada (ECCTD, 2009)

647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. - Benjamin Stefan Devlin; MyeongGyu Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2009)

Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links. - Mohamed Abbas; Kwang-Ting Cheng; Yasuo Furukawa; Satoshi Komatsu; Kunihiro Asada (ETS, 2009)

Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. - MyeongGyu Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ACM Great Lakes Symposium on VLSI, 2009)

Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability. - Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2009)

Cascaded time difference amplifier using differential logic delay cell. - Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2010)

An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. - Mohamed Abbas; Kwang-Ting Cheng; Yasuo Furukawa; Satoshi Komatsu; Kunihiro Asada (DATE, 2010)

Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. - Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (DDECS, 2010)

Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging. - Kunihiro Asada; Makoto Ikeda; Benjamin Stefan Devlin; Taku Sogabe (DFT, 2010)

All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. - Tetsuya Iizuka; Jaehyun Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2010)

Time-to-digital converter based on time difference amplifier with non-linearity calibration. - Shingo Mandai; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2010)

A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary. - Shingo Mandai; Makoto Ikeda; Kunihiro Asada (ISSCC, 2010)

A 8bit two stage time-to-digital converter using time difference amplifier. - Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Electron. Express, 2010)

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. - Benjamin Stefan Devlin; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Time Difference Amplifier with Robust Gain Using Closed-Loop Control. - Toru Nakura; Shingo Mandai; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2010)

A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2011)

All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. - Jaehyun Jeong; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2011)

A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS. - Nguyen Ngoc Mai Khanh; Masahiro Sasaki; Kunihiro Asada (ASP-DAC, 2011)

An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. - Tetsuya Iizuka; Kunihiro Asada (DDECS, 2011)

Decoupling capacitance boosting for on-chip resonant supply noise reduction. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (DDECS, 2011)

On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2011)

A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. - Kazutoshi Kodama; Tetsuya Iizuka; Kunihiro Asada (ESSCIRC, 2011)

Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology. - Mohamed Abbas; Takahiro J. Yamaguchi; Yasuo Furukawa; Satoshi Komatsu; Kunihiro Asada (ICECS, 2011)

All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS. - Sanad Bushnaq; Makoto Ikeda; Kunihiro Asada (ICECS, 2011)

Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (ICECS, 2011)

An equivalent-time and clocked approach for continuous-time quantization. - Takahiro J. Yamaguchi; Mohamed Abbas; Mani Soma; Takafumi Aoki; Yasuo Furukawa; Katsuhiko Degawa; Satoshi Komatsu; Kunihiro Asada (ISCAS, 2011)

Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (ISLPED, 2011)

Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy. - Teruki Nakasato; Toru Nakura; Kunihiro Asada (ISOCC, 2011)

Application of a continuous-time level crossing quantization method for timing noise measurements. - Takahiro J. Yamaguchi; Mani Soma; Takafumi Aoki; Yasuo Furukawa; Katsuhiko Degawa; Kunihiro Asada; Mohamed Abbas; Satoshi Komatsu (ITC, 2011)

All-digital ramp waveform generator for two-step single-slope ADC. - Tetsuya Iizuka; Kunihiro Asada (IEICE Electron. Express, 2011)

A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform. - Salih Ergün; Ülkühan Güler 001; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. - Tetsuya Iizuka; Jaehyun Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

A 0.18-µm CMOS X-Band Shock Wave Generator with an On-Chip Dipole Antenna and a Digitally Programmable Delay Circuit for Pulse Beam-Formability. - Nguyen Ngoc Mai Khanh; Masahiro Sasaki; Kunihiro Asada (IEICE Trans. Electron., 2011)

A 0.25-µm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging. - Nguyen Ngoc Mai Khanh; Masahiro Sasaki; Kunihiro Asada (IEICE Trans. Electron., 2011)

A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application. - Nguyen Ngoc Mai Khanh; Masahiro Sasaki; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. - Shingo Mandai; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method. - Shingo Mandai; Taihei Momma; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

Cascaded Time Difference Amplifier with Differential Logic Delay Cell. - Shingo Mandai; Toru Nakura; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation. - Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (J. Next Gener. Inf. Technol., 2011)

A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (IEEE J. Solid State Circuits, 2011)

Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (ASYNC, 2012)

Impact of All-Digital PLL on SoC Testing. - Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (Asian Test Symposium, 2012)

A New Procedure for Measuring High-Accuracy Probability Density Functions. - Takahiro J. Yamaguchi; Kunihiro Asada; Kiichi Niitsu; Mohamed Abbas; Satoshi Komatsu; Haruo Kobayashi 001; Jose A. Moreira (Asian Test Symposium, 2012)

7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. - Toru Nakura; Yoshio Mita; Tetsuya Iizuka; Kunihiro Asada (CICC, 2012)

Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (COOL Chips, 2012)

Range extension of inductive coupling communication using multi-stage resonance. - Sanad Bushnaq; Makoto Ikeda; Kunihiro Asada (ISCIT, 2012)

A design-for-test apparatus for measuring on-chip temperature with fine granularity. - James S. Tandon; Masahiro Sasaki; Makoto Ikeda; Kunihiro Asada (ISQED, 2012)

Power integrity control of ATE for emulating power supply fluctuations on customer environment. - Masahiro Ishida; Toru Nakura; Toshiyuki Kikkawa; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (ITC, 2012)

All-digital tunable power amplifier consuming 0.03mW/MHz using 0.18µm CMOS. - Sanad Bushnaq; Makoto Ikeda; Kunihiro Asada (IEICE Electron. Express, 2012)

All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction. - Sanad Bushnaq; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2012)

All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. - Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Electron., 2012)

A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. - Tetsuya Iizuka; Satoshi Miura; Ryota Yamamoto; Yutaka Chiba; Shunichi Kubo; Kunihiro Asada (IEICE Trans. Electron., 2012)

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2012)

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. - Kazutoshi Kodama; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (IEICE Trans. Electron., 2012)

Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter. - Toru Nakura; Kunihiro Asada (IEICE Trans. Electron., 2012)

High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. - Rimon Ikeno; Takashi Maruyama; Tetsuya Iizuka; Satoshi Komatsu; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2013)

A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC. - Tetsuya Iizuka; Satoshi Miura; Yohei Ishizone; Yoshimichi Murakami; Kunihiro Asada (CICC, 2013)

An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. - Tetsuya Iizuka; Teruki Someya; Toru Nakura; Kunihiro Asada (CICC, 2013)

A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. - James S. Tandon; Takahiro J. Yamaguchi; Satoshi Komatsu; Kunihiro Asada (CICC, 2013)

A Pulse Width controlled PLL and its automated design flow. - Norihito Tohge; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2013)

Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator. - Tomohiko Yano; Toru Nakura; Kunihiro Asada (ICECS, 2013)

A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. - Rimon Ikeno; Takashi Maruyama; Satoshi Komatsu; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (ISPD, 2013)

A novel test structure for measuring the threshold voltage variance in MOSFETs. - Takahiro J. Yamaguchi; James S. Tandon; Satoshi Komatsu; Kunihiro Asada (ITC, 2013)

Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments. - Benjamin Stefan Devlin; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2013)

High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. - Rimon Ikeno; Takashi Maruyama; Satoshi Komatsu; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. - Jinmyoung Kim; Toru Nakura; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2013)

A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge. - Takahiro J. Yamaguchi; James S. Tandon; Satoshi Komatsu; Kunihiro Asada (ATS, 2014)

Burst-pulse Generator based on transmission line toward sub-MMW. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Toru Nakura; Kunihiro Asada (DDECS, 2014)

Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. - Kevin Ngari Muriithi; Toru Nakura; Kunihiro Asada (DDECS, 2014)

Streaming distribution of a live seminar: Rudimentary knowledge for LSI design. - Toru Nakura; Kunihiro Asada (EWME, 2014)

A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique. - Hongbo Zhu; Kunihiro Asada (ICECS, 2014)

A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer. - James S. Tandon; Takahiro J. Yamaguchi; Satoshi Komatsu; Kunihiro Asada (ISCAS, 2014)

Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. - Masahiro Ishida; Takashi Kusaka; Toru Nakura; Satoshi Komatsu; Kunihiro Asada (ITC, 2014)

High-resolution measurement of magnetic field generated from cryptographic LSIs. - Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Akihiko Sasaki; Makoto Yamada; Osamu Morita; Kunihiro Asada (SAS, 2014)

A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. - Rimon Ikeno; Takashi Maruyama; Satoshi Komatsu; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters. - Satoshi Komatsu; Takahiro J. Yamaguchi; Mohamed Abbas; Nguyen Ngoc Mai Khanh; James S. Tandon; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. - Tomohiko Yano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (A-SSCC, 2015)

A Technique for Analyzing On-Chip Power Supply Impedance. - Masahiro Ishida; Toru Nakura; Akira Matsukawa; Rimon Ikeno; Kunihiro Asada (ATS, 2015)

An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. - Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (DDECS, 2015)

Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. - Takashi Toi; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (NORCAS, 2015)

Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline. - Toru Nakura; Hiroaki Matsui; Kunihiro Asada (IEICE Electron. Express, 2015)

Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer. - Toru Nakura; Masahiro Kano; Masamitsu Yoshizawa; Atsunori Hattori; Kunihiro Asada (IEICE Trans. Electron., 2015)

A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs. - Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Akihiko Sasaki; Makoto Yamada; Osamu Morita; Kunihiro Asada (IEEE Trans. Instrum. Meas., 2015)

A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. - Tetsuya Iizuka; Takehisa Koga; Toru Nakura; Kunihiro Asada (A-SSCC, 2016)

Analytical design optimization of sub-ranging ADC based on stochastic comparator. - Md. Maruf Hossain; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (DATE, 2016)

A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. - Tetsuya Iizuka; Norihito Tohge; Satoshi Miura; Yoshimichi Murakami; Toru Nakura; Kunihiro Asada (ESSCIRC, 2016)

One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise. - Toru Nakura; Yuki Okamoto; Yoshio Mita; Kunihiro Asada (EWME, 2016)

Resonant power supply noise reduction using a triangular active charge injection. - Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2016)

Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. - Nguyen Ngoc Mai Khanh; Rimon Ikeno; Takahiro J. Yamaguchi; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2016)

Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise. - Masahiro Kano; Toru Nakura; Kunihiro Asada (ISQED, 2016)

Fully automated PLL compiler generating final GDS from specification. - Toru Nakura; Kunihiro Asada (ISQED, 2016)

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. - Toru Nakura; Naoki Terao; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (ITC, 2016)

A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators. - James S. Tandon; Satoshi Komatsu; Takahiro J. Yamaguchi; Kunihiro Asada (NEWCAS, 2016)

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. - Masahiro Ishida; Toru Nakura; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (J. Electron. Test., 2016)

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. - Masahiro Ishida; Toru Nakura; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (IEICE Trans. Electron., 2016)

An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface. - Toshiyuki Kikkawa; Toru Nakura; Kunihiro Asada (IEICE Trans. Electron., 2016)

An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. - Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (J. Circuits Syst. Comput., 2016)

CMOS-on-quartz pulse generator for low power applications. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (ASP-DAC, 2017)

A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. - Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ASP-DAC, 2017)

High Spatial Resolution Detection Method for Point Light Source in Scintillator. - Kai Xu; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (Computational Imaging, 2017)

Extension of power supply impedance emulation method on ATE for multiple power domain. - Naoki Terao; Toru Nakura; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (ETS, 2017)

An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. - Ryuichi Enomoto; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (ICECS, 2017)

A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. - Takaaki Ito; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (ICECS, 2017)

A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. - Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2017)

A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. - Xiao Yang; Kai Xu; Tetsuya Iizuka; Toru Nakura; Hongbo Zhu; Kunihiro Asada (IEEE SENSORS, 2017)

Impulse signal generator based on current-mode excitation and transmission line resonator. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (NEWCAS, 2017)

Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A CMOS Broadband Transceiver with On-Chip Antenna Array and Built-In Pulse-Delay Calibration for Millimeter-Wave Imaging Applications. - Nguyen Ngoc Mai Khanh; Kunihiro Asada (IEICE Trans. Electron., 2017)

A PLL Compiler from Specification to GDSII. - Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. - Tomohiko Yano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Electron., 2017)

A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Rimon Ikeno; Takahiro J. Yamaguchi; Tetsuya Iizuka; Kunihiro Asada (MWSCAS, 2018)

A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. - Naoki Ojima; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (VLSI-SoC, 2018)

A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. - Naoki Ojima; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (VLSI-SoC (Selected Papers), 2018)

Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. - Naoki Terao; Toru Nakura; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (J. Electron. Test., 2018)

Time-domain approach for analog circuits in deep sub-micron LSI. - Kunihiro Asada; Toru Nakura; Tetsuya Iizuka; Makoto Ikeda (IEICE Electron. Express, 2018)

Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. - Md. Maruf Hossain; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. - Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Electron., 2018)

Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. - Toru Nakura; Tsukasa Kagaya; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Electron., 2018)

Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation. - Nguyen Ngoc Mai Khanh; Shigeru Nakajima; Tetsuya Iizuka; Yoshio Mita; Kunihiro Asada (IEEE Trans. Instrum. Meas., 2018)

Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. - Tetsuya Iizuka; Kai Xu; Xiao Yang; Toru Nakura; Kunihiro Asada (IEICE Electron. Express, 2019)

Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. - Daigo Takahashi; Tetsuya Iizuka; Nguyen Ngoc Mai Khanh; Toru Nakura; Kunihiro Asada (IEEE Trans. Instrum. Meas., 2019)

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. - Ryuichi Enomoto; Tetsuya Iizuka; Takehisa Koga; Toru Nakura; Kunihiro Asada (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper. - Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Kunihiro Asada (ICICDT, 2021)

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. - Tetsuya Iizuka; Meikan Chin; Toru Nakura; Kunihiro Asada (IEICE Trans. Electron., 2022)