The Totally-Perfect Bipartite Graph and Its Construction. - Kunihiro Fujiyoshi; Yoji Kajitani; Hiroshi Niitsu (ISAAC, 1994)

Design of Optimum Totally Perfect Connection-Blocks of FPGA. - Kunihiro Fujiyoshi; Yoji Kajitani; Hiroshi Niitsu (ISCAS, 1994)

Rectangle-packing-based module placement. - Hiroshi Murata; Kunihiro Fujiyoshi; Shigetoshi Nakatake; Yoji Kajitani (ICCAD, 1995)

Module placement on BSG-structure and IC layout applications. - Shigetoshi Nakatake; Kunihiro Fujiyoshi; Hiroshi Murata; Yoji Kajitani (ICCAD, 1996)

VLSI module placement based on rectangle-packing by the sequence-pair. - Hiroshi Murata; Kunihiro Fujiyoshi; Shigetoshi Nakatake; Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

A mapping from sequence-pair to rectangular dissection. - Hiroshi Murata; Kunihiro Fujiyoshi; Tomomi Watanabe; Yoji Kajitani (ASP-DAC, 1997)

Design of minimum and uniform bipartites for optimum connection blocks of FPGA. - Kunihiro Fujiyoshi; Yoji Kajitani; Hiroshi Niitsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

VLSI/PCB placement with obstacles based on sequence pair. - Hiroshi Murata; Kunihiro Fujiyoshi; Mineo Kaneko (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Module packing based on the BSG-structure and IC layout applications. - Shigetoshi Nakatake; Kunihiro Fujiyoshi; Hiroshi Murata; Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Arbitrary convex and concave rectilinear block packing using sequence-pair. - Kunihiro Fujiyoshi; Hiroshi Murata (ISPD, 1999)

Simulated annealing search through general structure floorplans using sequence-pair. - Koji Kiyota; Kunihiro Fujiyoshi (ISCAS, 2000)

Arbitrary convex and concave rectilinear block packing usingsequence-pair. - Kunihiro Fujiyoshi; Hiroshi Murata (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

An efficient decoding method of sequence-pair. - Chikaaki Kodama; Kunihiro Fujiyoshi (APCCAS (2), 2002)

An improved method of convex-shaped block packing based on sequence-pair [VLSI layout]. - Hiroaki Saito; Kazuya Wakata; Kunihiro Fujiyoshi; Keishi Sakanushi; Takayuki Obata (APCCAS (2), 2002)

An Efficient Decoding Method of Sequence-Pair with Reduced Redundancy. - Chikaaki Kodama; Kunihiro Fujiyoshi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pair. - Chikaaki Kodama; Kunihiro Fujiyoshi (ASP-DAC, 2003)

An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair. - Kazuya Wakata; Hiroaki Saito; Kunihiro Fujiyoshi; Keishi Sakanushi; Takayuki Obata; Chikaaki Kodama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A novel encoding method into sequence-pair. - Chikaaki Kodama; Kunihiro Fujiyoshi; Teppei Koga (ISCAS (5), 2004)

A Graph Based Soft Module Handling in Floorplan. - Hiroaki Itoga; Chikaaki Kodama; Kunihiro Fujiyoshi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge. - Chikaaki Kodama; Kunihiro Fujiyoshi (IEICE Trans. Inf. Syst., 2005)

Thermal Driven Module Placement Using Sequence-pair. - Norihide Okada; Chikaaki Kodama; Takashi Sato 001; Kunihiro Fujiyoshi (APCCAS, 2006)

Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. - Yukihide Kohira; Chikaaki Kodama; Kunihiro Fujiyoshi; Atsushi Takahashi 001 (ISCAS, 2006)

Improved method of cell placement with symmetry constraints for analog IC layout design. - Shinichi Kouda; Chikaaki Kodama; Kunihiro Fujiyoshi (ISPD, 2006)

DTS: A Tree Based Representation for 3D-Block Packing. - Kunihiro Fujiyoshi; Hidenori Kawai; Keisuke Ishihara (ISCAS, 2007)

A fast algorithm for rectilinear block packing based on selected sequence-pair. - Kunihiro Fujiyoshi; Chikaaki Kodama; Akira Ikeda (Integr., 2007)

Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout. - Shinichi Koda; Chikaaki Kodama; Kunihiro Fujiyoshi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

The O-Sequence: Representation of 3D-Dissection. - Hidenori Ohta; Toshinori Yamada; Chikaaki Kodama; Kunihiro Fujiyoshi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Representation of 3D-LSI Floorplan based on Stacked-rectangular-dissection. - Hidenori Ohta; Kunihiro Fujiyoshi (ISCAS, 2009)

Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation. - Natsumi Hirakawa; Kunihiro Fujiyoshi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A Tree Based Novel Representation for 3D-Block Packing. - Kunihiro Fujiyoshi; Hidenori Kawai; Keisuke Ishihara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

On the Number of Rooms in a Rectangular Solid Dissection. - Hidenori Ohta; Toshinori Yamada; Kunihiro Fujiyoshi (J. Inf. Process., 2010)

A novel representation for repeated placement. - Kunihiro Fujiyoshi; Keisuke Ishihara; Tan Wei Liang (ISCAS, 2011)

An efficient solution space for floorplan of 3D-LSI. - Hiroshi Tezuka; Kunihiro Fujiyoshi (ICECS, 2012)

Adjacent common centroid placement for analog IC layout design. - Kenichiro Murotatsu; Kunihiro Fujiyoshi (APCCAS, 2014)

Average placement method with common centroid constraints for analog IC layout design. - Kunihiro Fujiyoshi; Keitaro Ue (MWSCAS, 2014)

A Method of Analog IC Placement with Common Centroid Constraints. - Keitaro Ue; Kunihiro Fujiyoshi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A method for photo-diode array partitioning problem. - Kunihiro Fujiyoshi; Takahisa Imano (MWSCAS, 2016)

Photo-Diode Array Partitioning Problem for a Rectangular Region. - Kunihiro Fujiyoshi; Takahisa Imano (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Necessary and Sufficient Condition to Generate Representative Clip for Edge-Constrained Clustering of Layout Pattern Classification Problem. - Kunihiro Fujiyoshi; Tomoya Masutani (NEWCAS, 2023)

An improved method for a set-pair routing problem by SAT. - Koki Nagakura; Kunihiro Fujiyoshi (APCCAS, 2024)

Node-to-Node and Node-to-Set Disjoint Paths Problems in Bicubes. - Arata Kaneko; Htoo Htoo Sandi Kyaw; Kunihiro Fujiyoshi; Keiichi Kaneko (IEICE Trans. Inf. Syst., 2024)

A Method for Selecting the Wiring Direction from Terminals using a Planar Graph Drawing Method. - Takuto Amari; Heihachirou Hasumi; Kunihiro Fujiyoshi (ISCAS, 2025)

Fault-Tolerant Routing in Bicubes. - Yitong Wang; Htoo Htoo Sandi Kyaw; Kunihiro Fujiyoshi; Keiichi Kaneko (IEICE Trans. Inf. Syst., 2025)

Polygon Fracture Method Considering Maximum Shot Size for Variable Shaped-beam Mask Writing. - Mitsuru Hasegawa; Taiki Matsuzaki; Kunihiro Fujiyoshi (IPSJ Trans. Syst. LSI Des. Methodol., 2025)