A 256-Mb SDRAM using a register-controlled digital DLL. - Atsushi Hatakeyama; Hirohiko Mochizuki; Tadao Aikawa; Masato Takita; Yuki Ishii; Hironobu Tsuboi; Shin-ya Fujioka; Shusaku Yamaguchi; Makoto Koga; Yuji Serizawa; Koichi Nishimura; Kuninori Kawabata; et al. (IEEE J. Solid State Circuits, 1997)

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line. - Satoshi Eto; Masato Matsumiya; Masato Takita; Yuki Ishii; Toshikazu Nakamura; Kuninori Kawabata; Hideki Kano; Ayako Kitamoto; Toshimi Ikeda; Toru Koga; Mitsuhiro Higashiho; Yuji Serizawa; et al. (IEEE J. Solid State Circuits, 1998)

An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology. - Shoichiro Kawashima; Keizo Morita; Mitsuharu Nakazawa; Kazuaki Yamane; Mitsuhiro Ogai; Kuninori Kawabata; Kazuaki Takai; Yasuhiro Fujii; Ryoji Yasuda; Wensheng Wang; Yukinobu Hikosaka; Ken'ichi Inoue (IEICE Trans. Electron., 2015)

Development of 16 Mb NRAM Aiming for High Reliability, Small Cell Area, and High Switching Speed. - Hitoshi Saito; Jun'ichi Watanabe; J. Seino; Tetsuro Tamura; Naoya Sashida; Kota Hara; Kuninori Kawabata; Atsushi Fujii; Jun Ohno; Atsushi Nakakubo; Manabu Kojima; T. Shimoyama; et al. (IMW, 2021)