Design of a second-level cache chip for shared-bus multimicroprocessor systems. - Kunio Uchiyama; Hirokazu Aoki; Osamu Nishii; Susumu Hatano; Osamu Nagashima; Kanji Oishi; Jun Kitano (IEEE J. Solid State Circuits, 1991)

Design Methodology for GMICROTM/500 TRON Microprocessor. - Susumu Narita; Fumio Arakawa; Kunio Uchiyama; Ikuya Kawasaki (ICCD, 1993)

The Gmicro/500 superscalar microprocessor with branch buffers. - Kunio Uchiyama; Fumio Arakawa; Susumu Narita; Hirokazu Aoki; Ikuya Kawasaki; Shigezumi Matsui; Mitsuyoshi Yamamoto; Norio Nakagawa; Ikuo Kudo (IEEE Micro, 1993)

A PA-RISC Mikroprocessor PA/50L For Low-Cost Systems. - Tetsuhiko Okada; Susumu Narita; Osamu Nishii; Noriharu Hiratsuka; Nobuyuki Hayashi; Mitsuo Asai; Shinji Fujiwara; Mikiko Satoh; Junichi Nishimoto; Hirokazu Aoki; Kunio Uchiyama; Shigeru Matsuo; et al. (COMPCON, 1994)

Functional verification of the superscalar SH-4 microprocessor. - Prasenjit Biswas; Andy Freeman; Kouji Yamada; Norio Nakagawa; Kunio Uchiyama (COMPCON, 1997)

Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. - Toshihiro Hattori; Yusuke Nitta; Mitsuho Seki; Susumu Narita; Kunio Uchiyama; Tsuyoshi Takahashi; Ryuichi Satomura (DAC, 1998)

SH4 RISC multimedia microprocessor. - Fumio Arakawa; Osamu Nishii; Kunio Uchiyama; Norio Nakagawa (IEEE Micro, 1998)

An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode. - Hiroyuki Mizuno; Koichiro Ishibashi; Takanori Shimura; Toshihiro Hattori; Susumu Narita; Kenji Shiozawa; Shuji Ikeda; Kunio Uchiyama (IEEE J. Solid State Circuits, 1999)

SH-5: The 64-Bit SuperH Architecture. - Prasenjit Biswas; Atsushi Hasegawa; Srinivas Mandaville; Mark Debbage; Andy Sturges; Fumio Arakawa; Yasuhiko Saito; Kunio Uchiyama (IEEE Micro, 2000)

Guest Editors' Introduction: Energy-Efficient Design. - Kunio Uchiyama; Pradip Bose (IEEE Micro, 2005)

Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. - Keisuke Toyama 003; Satoshi Misaka; Kazuo Aisaka; Toshiyuki Aritsuka; Kunio Uchiyama; Koichiro Ishibashi; Hiroshi Kawaguchi 001; Takayasu Sakurai (Syst. Comput. Jpn., 2005)

Power-Efficient Heterogeneous Multicore Technology for Digital Convergence. - Kunio Uchiyama (Asia-Pacific Computer Systems Architecture Conference, 2007)

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. - Yutaka Yoshida; Tatsuya Kamei; Kiyoshi Hayase; Shinichi Shibahara; Osamu Nishii; Toshihiro Hattori; Atsushi Hasegawa; Masashi Takada; Naohiko Irie; Kunio Uchiyama; Toshihiko Odaka; Kiwamu Takada; et al. (ISSCC, 2007)

Software-cooperative power-efficient heterogeneous multi-core for media processing. - Hiroaki Shikano; Masaki Ito; Kunio Uchiyama; Toshihiko Odaka; Akihiro Hayashi; Takeshi Masuura; Masayoshi Mase; Jun Shirako; Yasutaka Wada; Keiji Kimura; Hironori Kasahara (ASP-DAC, 2008)

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. - Masayuki Ito; Toshihiro Hattori; Yutaka Yoshida; Kiyoshi Hayase; Tomoichi Hayashi; Osamu Nishii; Yoshihiko Yasu; Atsushi Hasegawa; Masashi Takada; Hiroyuki Mizuno; Kunio Uchiyama; Toshihiko Odaka; et al. (ISSCC, 2008)

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. - Hiroaki Shikano; Masaki Ito; Masafumi Onouchi; Takashi Todaka; Takanobu Tsunoda; Tomoyuki Kodama; Kunio Uchiyama; Toshihiko Odaka; Tatsuya Kamei; Ei Nagahama; Manabu Kusaoke; Yusuke Nitta; et al. (IEEE J. Solid State Circuits, 2008)

A 45nm 37.3GOPS/W heterogeneous multi-core SoC. - Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Shigezumi Matsui; Osamu Nishii; Atsushi Hasegawa; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Koichi Terada; Tohru Nojiri; et al. (ISSCC, 2010)

Foreword. - Kunio Uchiyama (IEICE Trans. Electron., 2010)

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. - Yoshitaka Hiramatsu; Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Tohru Nojiri; Kunio Uchiyama; Michitaka Kameyama (IEICE Trans. Electron., 2012)

Society 5.0: For Human Security and Well-Being. - Yoshihiro Shiroishi; Kunio Uchiyama; Norihiro Suzuki (Computer, 2018)

Better Actions for Society 5.0: Using AI for Evidence-Based Policy Making That Keeps Humans in the Loop. - Yoshihiro Shiroishi; Kunio Uchiyama; Norihiro Suzuki (Computer, 2019)

Edge Artificial Intelligence Chips for the Cyberphysical Systems Era. - Hiroshi Fuketa; Kunio Uchiyama (Computer, 2021)

SoC Platform for Heterogeneous Accelerator IPs SoC development platform for evaluation and demonstration. - Atsushi Hasegawa; Makoto Ikeda; Ichiro Naka; Kunio Uchiyama (ISOCC, 2024)