Complexity-effective dynamic range compression for digital hearing aids. - Kuo-Chiang Chang; Yu-Ting Kuo; Tay-Jyi Lin; Chih-Wei Liu (ISCAS, 2010)

Complexity-effective auditory compensation with a controllable filter for digital hearing aids. - Ya-Ting Chang; Kuo-Chiang Chang; Yu-Ting Kuo; Chih-Wei Liu (ASP-DAC, 2012)

A low power hearing aid computing platform using lightweight processing elements. - Kuo-Chiang Chang; Yu-Wen Chen; Yu-Ting Kuo; Chih-Wei Liu (ISCAS, 2012)

An object tracking scheme for wireless sensor networks using data mining mechanism. - Wen-Hwa Liao; Kuo-Chiang Chang; Sital Prasad Kedia (NOMS, 2012)

Design and implementation of 18-band Quasi-ANSI S1.11 1/3-octave filter bank for digital hearing aids. - Ching-Hao Lin; Kuo-Chiang Chang; Ming-Hsun Chuang; Chih-Wei Liu (VLSI-DAT, 2012)

Spatial-cue-based multi-band binaural noise reduction for hearing aids. - Cheng-Yen Yang; Wen-Sheng Chou; Kuo-Chiang Chang; Chih-Wei Liu; Tai-Shih Chi; Shyh-Jye Jou (SiPS, 2013)

10-ms 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank for Digital Hearing Aids. - Chih-Wei Liu; Kuo-Chiang Chang; Ming-Hsun Chuang; Ching-Hao Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

An ultra-low voltage hearing aid chip using variable-latency design technique. - Kuo-Chiang Chang; Shien-Chun Luo; Ching-Ji Huang; Chih-Wei Liu; Yuan-Hua Chu; Shyh-Jye Jou (ISCAS, 2014)

Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier. - Kuo-Chiang Chang; Ching-Hao Lin; Chih-Wei Liu (VLSI-DAT, 2014)

Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. - Shien-Chun Luo; Kuo-Chiang Chang; Ming-Pin Chen; Ching-Ji Huang; Yi-Fang Chiu; Po-Hsun Chen; Liang-Chia Cheng; Chih-Wei Liu; Yuan-Hua Chu (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids. - Shih-Hao Ou; Kuo-Chiang Chang; Chih-Wei Liu (Integr., 2015)

A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor. - Chih-Wei Liu; Shih-Hao Ou; Kuo-Chiang Chang; Tsung-Ching Lin; Shin-Kai Chen (IEEE Trans. Computers, 2016)

MORAS: An energy-scalable system using adaptive voltage scaling. - Kuo-Chiang Chang; Shien-Chun Luo; Ching-Ji Huang; Jia-Hung Peng; Yuan-Hua Chu (VLSI-DAT, 2018)

Configurable Deep Learning Accelerator with Bitwise-accurate Training and Verification. - Shien-Chun Luo; Kuo-Chiang Chang; Po-Wei Chen; Zhao-Hong Chen (VLSI-DAT, 2022)