MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. - W.-C. Lin; H.-P. Huang; Kuo-Hsing Kao; Meng-Hsueh Chiang; Darsen D. Lu; Wei-Chou Hsu; Yeong-Her Wang; William Cheng-Yu Ma; Hann-Huei Tsai; Y.-J. Lee; H.-L. Chiang; J.-F. Wang; et al. (ESSDERC, 2023)

Insight into Latchup Risk in 28nm Planar Bulk Technology for Quantum Computing Applications. - Kateryna Serbulova; Zi-En Qiu; Shih-Hung Chen; Alexander Grill; Kuo-Hsing Kao; Jo De Boeck; Guido Groeseneken (IRPS, 2024)

Numerical Simulations of Gate-Granularity- Induced Subthreshold Characteristics Deterioration of MOSFETs Magnified at Cryogenic Temperatures. - Kuo-Hsing Kao; Zong-Hong Wang; Yu-Chia Pai; Chen-Chi Cheng; Darsen D. Lu; Wen-Jay Lee; Nan-Yow Chen (IEEE Access, 2024)