Error Catch and Analysis for Semiconductor Memories Using March Tests. - Chi-Feng Wu; Chih-Tsun Huang; Chih-Wea Wang; Kuo-Liang Cheng; Cheng-Wen Wu (ICCAD, 2000)

Simulation-Based Test Algorithm Generation for Random Access Memories. - Chi-Feng Wu; Chih-Tsun Huang; Kuo-Liang Cheng; Cheng-Wen Wu (VTS, 2000)

Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. - Kuo-Liang Cheng; Chia-Ming Hsueh; Jing-Reng Huang; Jen-Chieh Yeh; Chih-Tsun Huang; Cheng-Wen Wu (Asian Test Symposium, 2001)

Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. - Chi-Feng Wu; Chih-Tsun Huang; Kuo-Liang Cheng; Chih-Wea Wang; Cheng-Wen Wu (DAC, 2001)

March-based RAM diagnosis algorithms for stuck-at and coupling faults. - Jin-Fu Li 001; Kuo-Liang Cheng; Chih-Tsun Huang; Cheng-Wen Wu (ITC, 2001)

Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. - Kuo-Liang Cheng; Ming-Fu Tsai; Cheng-Wen Wu (VTS, 2001)

Test Scheduling and Test Access Architecture Optimization for System-on-Chip. - Huan-Shan Hsu; Jing-Reng Huang; Kuo-Liang Cheng; Chih-Wea Wang; Chih-Tsun Huang; Cheng-Wen Wu; Youn-Long Lin (Asian Test Symposium, 2002)

Test Scheduling of BISTed Memory Cores for SOC. - Chih-Wea Wang; Jing-Reng Huang; Yen-Fu Lin; Kuo-Liang Cheng; Chih-Tsun Huang; Cheng-Wen Wu; Youn-Long Lin (Asian Test Symposium, 2002)

Flash Memory Built-In Self-Test Using March-Like Algorithm. - Jen-Chieh Yeh; Chi-Feng Wu; Kuo-Liang Cheng; Yung-Fa Chou; Chih-Tsun Huang; Cheng-Wen Wu (DELTA, 2002)

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. - Kuo-Liang Cheng; Jen-Chieh Yeh; Chih-Wea Wang; Chih-Tsun Huang; Cheng-Wen Wu (VTS, 2002)

Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. - Kuo-Liang Cheng; Ming-Fu Tsai; Cheng-Wen Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Fault simulation and test algorithm generation for random accessmemories. - Chi-Feng Wu; Chih-Tsun Huang; Kuo-Liang Cheng; Cheng-Wen Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

FAME: A Fault-Pattern Based Memory Failure Analysis Framework. - Kuo-Liang Cheng; Chih-Wea Wang; Jih-Nung Lee; Yung-Fa Chou; Chih-Tsun Huang; Cheng-Wen Wu (ICCAD, 2003)

Fault Pattern Oriented Defect Diagnosis for Memories. - Chih-Wea Wang; Kuo-Liang Cheng; Jih-Nung Lee; Yung-Fa Chou; Chih-Tsun Huang; Cheng-Wen Wu; Frank Huang; Hong-Tzer Yang (ITC, 2003)

Test and Diagnosis of Word-Oriented Multiport Memories. - Chih-Wea Wang; Kuo-Liang Cheng; Chih-Tsun Huang; Cheng-Wen Wu (VTS, 2003)

An SOC Test Integration Platform and Its Industrial Realization. - Kuo-Liang Cheng; Jing-Reng Huang; Chih-Wea Wang; Chih-Yen Lo; Li-Ming Denq; Chih-Tsun Huang; Shin-Wei Hung; Jye-Yuan Lee (ITC, 2004)

Design and test of a scalable security processor. - Chih-Pin Su; Chen-Hsing Wang; Kuo-Liang Cheng; Chih-Tsun Huang; Cheng-Wen Wu (ASP-DAC, 2005)

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. - Jen-Chieh Yeh; Kuo-Liang Cheng; Yung-Fa Chou; Cheng-Wen Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

STEAC: A Platform for Automatic SOC Test Integration. - Chih-Yen Lo; Chen-Hsing Wang; Kuo-Liang Cheng; Jing-Reng Huang; Chih-Wea Wang; Shin-Moe Wang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2007)