Dynamically reconfigurable regular expression matching architecture. - J. Divyasree; H. Rajashekar; Kuruvilla Varghese (ASAP, 2008)

A Scalable High Throughput Firewall in FPGA. - Gajanan S. Jedhe; Arun Ramamoorthy; Kuruvilla Varghese (FCCM, 2008)

Power optimal Network-on-Chip interconnect design. - G. Vikas; Joy Kuri; Kuruvilla Varghese (SoCC, 2009)

Area optimized H.264 Intra prediction architecture for 1080p HD resolution. - Jimit Shah; K. S. Raghunandan 001; Kuruvilla Varghese (ASAP, 2010)

Space Efficient Diagonal Linear Space Sequence Alignment. - Gandhi Arpit; Raghavendra Adiga; Kuruvilla Varghese (BIBE, 2010)

In-channel Flow Control Scheme for Network-on-Chip. - Vrishali Vijay Nimbalkar; Kuruvilla Varghese (DSD, 2010)

A scalable network port scan detection system on FPGA. - Tejasvi Anand; Yagnesh Waghela; Kuruvilla Varghese (FPT, 2011)

HD Resolution Intra Prediction Architecture for H.264 Decoder. - Jimit Shah; K. S. Raghunandan 001; Kuruvilla Varghese (VLSI Design, 2012)

Transparent FPGA based device for SQL DDoS mitigation. - Karthikeyan Pandiyarajan; Srijith Haridas; Kuruvilla Varghese (FPT, 2013)

Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA. - Sriram Venkateshan; Alap Patel; Kuruvilla Varghese (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA. - Saugata Datta; Kuruvilla Varghese; Shayan Garani Srinivasa (VLSID, 2016)

A high-throughput clock-less architecture for soft-output Viterbi detection. - Arnab Dey; Sebin Jose; Kuruvilla Varghese; Shayan Garani Srinivasa (MWSCAS, 2017)

A Custom Designed RISC-V ISA Compatible Processor for SoC. - Kavya Sharat; Sumeet Bandishte; Kuruvilla Varghese; Bharadwaj S. Amrutur (VDAT, 2017)

FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training. - Sajna Remi Clere; Sachin Sethumadhavan; Kuruvilla Varghese (DSD, 2018)

Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network. - Nimish Shah; Paragkumar Chaudhari; Kuruvilla Varghese (IEEE Trans. Neural Networks Learn. Syst., 2018)

Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA. - T. Gokulan; Akshay Muraleedharan; Kuruvilla Varghese (DSD, 2020)

A RISC-V ISA Compatible Processor IP. - Akshay Birari; Piyush Birla; Kuruvilla Varghese; Bharadwaj S. Amrutur (VDAT, 2020)

Network Emulation For Tele-driving Application Development. - Srikrishna Acharya; S. Sadgun S. Devanahalli; Alok Rawat; Kuruvilla Varghese; Pratik Sharma; Bharadwaj Amrutur; Ashish Joglekar; Raghu Krishnapuram; Yogesh Simmhan; Himanshu Tyagi (COMSNETS, 2021)

High-Level Synthesis of Geant4 Particle Transport Application for FPGA. - Ramakant Joshi; Kuruvilla Varghese (DSD, 2022)

A Soft RISC-V Vector Processor for Edge-AI. - V. Naveen Chander; Kuruvilla Varghese (VLSID, 2022)

Hardware Accelerator for Capsule Network based Reinforcement Learning. - Dola Ram; Suraj Panwar; Kuruvilla Varghese (VLSID, 2022)

Deep-Feature-Based Visual Odometry for Autonomous Emergency Parking. - Shrutheesh Raman Iyer; Kuruvilla Varghese; Raghu Krishnapuram; Panini Bhamidipati (AIR, 2023)

High Throughput Hardware Acceleration for Image Generation using HLS. - A. BhanuPrasad; Kuruvilla Varghese (APCCAS, 2023)

Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder. - Sadhu Sai Ram; Kuruvilla Varghese (APCCAS, 2023)

An FPGA Based Accelerator of the Bi-Directional Wavefront Algorithm for Pairwise Sequence Alignment. - Ajay S; Praveen V. S; Kuruvilla Varghese (APCCAS, 2023)

Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core. - Sajin S; Shubham Sunil Garag; Anuj Phegade; Deepshikha Gusain; Kuruvilla Varghese (VLSID, 2023)