Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs. - Kwan-Hee Jo; Ji-Hye Bong; Kyeong-Sik Min (IEICE Electron. Express, 2009)

A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs. - Kwan-Hee Jo; Ji-Hye Bong; Kyeong-Sik Min; Sung-Mo Kang (IEICE Electron. Express, 2009)

Memristor models and circuits for controlling Process-VDD-Temperature variations. - Kwan-Hee Jo; Chul-Moon Jung; Kyeong-Sik Min (ASICON, 2011)

Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits. - Ji-Hye Bong; Kwan-Hee Jo; Kyeong-Sik Min; Sung-Mo Kang (J. Low Power Electron., 2011)