A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL. - Dong-Uk Lee; Hyun-Woo Lee; Ki Chang Kwean; Young-Kyoung Choi; Hyong Uk Moon; Seung-Wook Kwack; Shin-Deok Kang; Kwan-Weon Kim; Yong Ju Kim; Young-Jung Choi; Patrick B. Moran; Jin-Hong Ahn; et al. (ISSCC, 2006)

A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC. - Dongsuk Shin; Janghoon Song; Hyunsoo Chae; Kwan-Weon Kim; Young-Jung Choi; Chulwoo Kim (ISSCC, 2007)

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface. - Dong-Uk Lee; Shin-Deok Kang; Nak-Kyu Park; Hyun-Woo Lee; Young-Kyoung Choi; Jung-Woo Lee; Seung-Wook Kwack; Hyeong-Ouk Lee; Won-Joo Yun; Sang-Hoon Shin; Kwan-Weon Kim; Young-Jung Choi; et al. (ISSCC, 2008)

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. - Won-Joo Yun; Hyun-Woo Lee; Dongsuk Shin; Shin-Deok Kang; Ji-Yeon Yang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; Young-Ju Kim 001; Won-Jun Choi; Keun-Soo Song; Sang-Hoon Shin; et al. (ISSCC, 2008)

Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application. - Jabeom Koo; Gil-Su Kim; Junyoung Song; Kwan-Weon Kim; Young-Jung Choi; Chulwoo Kim (CICC, 2009)

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. - Hyun-Woo Lee; Won-Joo Yun; Young-Kyoung Choi; Hyang-Hwa Choi; Jong-Jin Lee; Ki-Han Kim; Shin-Deok Kang; Ji-Yeon Yang; Jae-Suck Kang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; et al. (ISSCC, 2009)

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. - Hyun-Woo Lee; Yong-Hoon Kim; Won-Joo Yun; Eun Young Park; Kang Youl Lee; Jaeil Kim; Kwang Hyun Kim; Jongho Jung; Kyung Whan Kim; Nam Gyu Rye; Kwan-Weon Kim; Jun Hyun Chun; et al. (ISCAS, 2010)

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. - Hyun-Woo Lee; Ki-Han Kim; Young-Kyoung Choi; Ju-Hwan Shon; Nak-Kyu Park; Kwan-Weon Kim; Chulwoo Kim; Young-Jung Choi; Byong-Tae Chung (ISSCC, 2011)

A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology. - Hyun-Woo Lee; Ki-Han Kim; Young-Kyoung Choi; Ju-Hwan Sohn; Nak-Kyu Park; Kwan-Weon Kim; Chulwoo Kim; Young-Jung Choi; Byong-Tae Chung (IEEE J. Solid State Circuits, 2012)

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV. - Dong-Uk Lee; Kyung Whan Kim; Kwan-Weon Kim; Hongjung Kim; Ju Young Kim; Young Jun Park 006; Jae Hwan Kim; Dae Suk Kim; Heat Bit Park; Jin Wook Shin; Jang Hwan Cho; Ki Hun Kwon; et al. (ISSCC, 2014)

An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM. - Dong-Uk Lee; Kyung Whan Kim; Kwan-Weon Kim; Kang Seol Lee; Sang Jin Byeon; Jin-Hee Cho; Han Ho Jin; Sang Kyun Nam; Jaejin Lee; Jun Hyun Chun; Sung-Joo Hong (VLSIC, 2014)

A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits. - Dong-Uk Lee; Kyung Whan Kim; Kwan-Weon Kim; Kang Seol Lee; Sang Jin Byeon; Jae-Hwan Kim; Jin-Hee Cho; Jaejin Lee; Jun Hyun Chun (IEEE J. Solid State Circuits, 2015)