A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller. - Seong Ju Lee; Byung Deuk Jeon; Kyeong Pil Kang; Dong Yoon Ka; Na Yeon Kim; Yongseop Kim; Yunseok Hong; Mankeun Kang; Jinyong Min; Mingyu Lee; Chunseok Jeong; Kwandong Kim; et al. (ISSCC, 2019)

A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. - Moon-Chul Choi; Deog-Kyoon Jeong; Sung-Yong Cho; Minkyo Shim; Byungmin Kim; Han-Gon Ko; Haram Ju; Kwanseo Park; Hyojun Kim; Kwandong Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. - Hyojun Kim; Woosong Jung; Kwandong Kim; Sungwoo Kim 001; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2022)

A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. - Moon-Chul Choi; Sanghee Lee 002; Seungha Roh; Kwangho Lee; Jonghyun Oh; Sungwoo Kim 001; Kwandong Kim; Woo-Seok Choi; Jaeha Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)