A Precision Output Conductance Model for Analog CMOS Circuit Simulations. - Jong Kug Seon; Kwang Sub Yoon (ISCAS, 1995)

A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load. - Jai-Sop Hyun; Kwang Sub Yoon (Great Lakes Symposium on VLSI, 1996)

A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. - Hyuk-Jun Sung; Kwang Sub Yoon (ISCAS (2), 1999)

A dual band CMOS VCO with a balanced duty cycle buffer. - Yun Cheol Han; Kwang Il Kim; Jun Kim; Kwang Sub Yoon (ACM Great Lakes Symposium on VLSI, 2003)

Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. - Soo Jin Park; Byoung Hee Yoon; Kwang Sub Yoon; Heung Soo Kim (ISMVL, 2004)

Design of a 12-b asynchronous SAR CMOS ADC. - Jinwoo Kim; Shin-Il Lim; Kwang Sub Yoon; Sangmin Lee (ISOCC, 2011)

Design of high dimming ratio power-LED driver with preloading inductor current methodology. - Keon Lee; Dong-hun Lee; Su-hun Yang; Ji-hyun Park; Kwang Sub Yoon (ISOCC, 2012)

A CMOS high dimming ratio power-LED driver with a preloading inductor current method. - Kwang Sub Yoon; Keon Lee (ISQED, 2013)

Design of a low power CMOS 10bit flash-SAR ADC. - Gi-Yoon Lee; Kwang Sub Yoon (SoCC, 2014)

A CMOS hysteretic DC-DC buck converter with a low output ripple voltage. - Tae-Jin Chung; Kwang Sub Yoon (ISQED, 2015)

A CMOS 10-bit SAR ADC with threshold configuring comparator for 5 MSBs. - Sang Heon Lee; Seong Jae Hyeon; Kim Jong Gu; Kwang Sub Yoon (ISOCC, 2016)

A CMOS buck converter with PFM / hysteretic mode. - Tae-Heon Lee; Jong-Gu Kim; Kwang Sub Yoon (ISOCC, 2016)

A low power fourth order ΣΔ CMOS modulator with subthreshold amplifier. - Seong Jae Hyeon; Kwang Sub Yoon; Soo Hun Yang (SoCC, 2016)

A CMOS third order ΔΣ modulator with inverter-based integrators. - Jeong H. Choi; Kwang Sub Yoon (SoCC, 2017)