OCV-aware top-level clock tree optimization. - Tuck-Boon Chan; Kwangsoo Han; Andrew B. Kahng; Jae-Gon Lee; Siddhartha Nath (ACM Great Lakes Symposium on VLSI, 2014)

Benchmarking of mask fracturing heuristics. - Tuck-Boon Chan; Puneet Gupta 001; Kwangsoo Han; Abde Ali Kagalwalla; Andrew B. Kahng; Emile Sahouria (ICCAD, 2014)

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router. - Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001 (DAC, 2015)

A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. - Kwangsoo Han; Jiajia Li 002; Andrew B. Kahng; Siddhartha Nath; Jongpil Lee (DAC, 2015)

Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints. - Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001 (ICCAD, 2015)

Clock clustering and IO optimization for 3D integration. - Samyoung Bang; Kwangsoo Han; Andrew B. Kahng; Vaishnav Srinivas (SLIP, 2015)

Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products. - Samyoung Bang; Kwangsoo Han; Andrew B. Kahng; Mulong Luo (ASP-DAC, 2016)

Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking. - Kwangsoo Han; Andrew B. Kahng; Jiajia Li 002 (DATE, 2016)

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. - Peter Debacker; Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Praveen Raghavan; Lutong Wang (DAC, 2017)

Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI. - Changho Han; Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Lutong Wang; Bangqi Xu (ICCAD, 2017)

Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes. - Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Lutong Wang (ISQED, 2017)

Benchmarking of Mask Fracturing Heuristics. - Tuck-Boon Chan; Puneet Gupta 001; Kwangsoo Han; Abde Ali Kagalwalla; Andrew B. Kahng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. - Peter Debacker; Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Praveen Raghavan; Lutong Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions. - Kwangsoo Han; Andrew B. Kahng; Christopher Moyes; Alex Zelikovsky (SLIP@DAC, 2018)

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. - Charles J. Alpert; Wing-Kai Chow; Kwangsoo Han; Andrew B. Kahng; Zhuo Li 001; Derong Liu 002; Sriram Venkatesh (ISPD, 2018)

IC Physical Design Methodologies for Advanced Process Nodes - Kwangsoo Han (2018)

Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution. - Kwangsoo Han; Andrew B. Kahng; Jiajia Li 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

2024 ICCAD CAD Contest Problem A: Reinforcement Logic Optimization for a General Cost Function. - Chung-Han Chou; Chih-Jen Hsu; Chi-An Wu; Kuan-Hua Tu; Kwangsoo Han; Zhou Li (ICCAD, 2024)