High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study. - Hye-On Jang; Minsoo Kang; Myeong-jin Lee; Kwanyeob Chae; Kookpyo Lee; Kyuhyun Shim (DATE, 2004)

A dynamic timing control technique utilizing time borrowing and clock stretching. - Kwanyeob Chae; Saibal Mukhopadhyay; Chang-Ho Lee; Joy Laskar (CICC, 2010)

Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs. - Kwanyeob Chae; Saibal Mukhopadhyay (ASP-DAC, 2012)

Characterization of Inverse Temperature Dependence in logic circuits. - Minki Cho; Muhammad M. Khellah; Kwanyeob Chae; Khondker Zakir Ahmed 001; James W. Tschanz; Saibal Mukhopadhyay (CICC, 2012)

Low-power design under variation using error prevention and error tolerance (invited paper). - Kwanyeob Chae; Minki Cho; Saibal Mukhopadhyay (LATW, 2012)

All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in a Low-Voltage Operation. - Kwanyeob Chae; Saibal Mukhopadhyay (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Error resilient logic circuits under dynamic variations. - Kwanyeob Chae; Saibal Mukhopadhyay (IOLTS, 2013)

On the impact of 3D integration on high-throughput sensor information processing: A case study with image sensing. - Denny Lie; Kwanyeob Chae; Saibal Mukhopadhyay (NANOARCH, 2013)

A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching. - Kwanyeob Chae; Saibal Mukhopadhyay (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating. - Kwanyeob Chae; Saibal Mukhopadhyay (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology. - Kwanyeob Chae; JongRyun Choi; Shinyoung Yi 002; Won Lee; Sanghoon Joo; Hyunhyuck Kim; Hyungkwon Yi; Yoonjee Nam; Jinho Choi; Sanghune Park; Sanghyun Lee (ESSCIRC, 2016)

23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller. - Soo-Min Lee; Jihun Oh; Jinho Choi; Seokkyun Ko; Daero Kim; Kyounghoi Koo; JongRyun Choi; Yoonjee Nam; Sangsoo Park; Hyungkweon Lee; Eunsu Kim; Sukhyun Jung; et al. (ISSCC, 2017)

Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface. - Kwanyeob Chae; Billy Koo; Jihun Oh; Sanghune Park; Jongshin Shin; Jaehong Park (ISOCC, 2018)

An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. - Kwanyeob Chae; JongRyun Choi; Hyungkwon Lee; Jinho Choi; Shinyoung Yi 002; Yoonjee Nam; Sangyun Hwang; Joohyung Lee; Won Lee; Kihwan Seong; Joohee Shin; Soo-Min Lee; et al. (VLSI Circuits, 2019)

22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique. - Soo-Min Lee; Kihwan Seong; Joohee Shin; Hyoungjoong Kim; Jaehyun Jeong; Shinyoung Yi 002; Juyoung Kim; Eunsu Kim; Sukhyun Jung; Sangyun Hwang; Jihun Oh; Kwanyeob Chae; et al. (ISSCC, 2020)

A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. - Kwanyeob Chae; Jiyeon Park; Jaegeun Song; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Taekyung Yeo; Kyeongkeun Kang; Sangsoo Park; Eunsu Kim; et al. (ISSCC, 2023)

A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM. - Yoonjae Choi; Jaegeun Song; Daero Kim; Myunggon Kim; Jiyeon Park; Jinho Choi; Changki Kwon; Minho Seo; Jihun Oh; Shinyoung Yi 002; Billy Koo; Kwanyeob Chae; et al. (A-SSCC, 2024)

A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. - Kwanyeob Chae; Jaegeun Song; Yoonjae Choi; Jiyeon Park; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Kyeongkeun Kang; Eunsu Kim; Juyoung Kim; et al. (IEEE J. Solid State Circuits, 2024)