Wafer scale integration of Configurable, Highly Parallel (CHiP) processors. - Kye S. Hedlund; Lawrence Snyder 001 (ICPP, 1982)

Wafer scale integration of configurable, highly parallel processors - Kye S. Hedlund (1982)

Electrical optimization of PLAs. - Kye S. Hedlund (DAC, 1985)

Performance modeling in integrated curcuit design (tutorial). - Kye S. Hedlund (SIGMETRICS, 1986)

Aesop: A Tool for Automated Transistor Sizing. - Kye S. Hedlund (DAC, 1987)