A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth. - Jei-Hwan Yoo; Chang-Hyun Kim; Kyu-Chan Lee; Kye-Hyun Kyung; Seung-Moon Yoo; Jung-Hwa Lee; Moon-Hae Son; Jin-Man Han; Bok-Moon Kang; Ejaz Haq; Sang-Bo Lee; Jai-Hoon Sim; et al. (IEEE J. Solid State Circuits, 1996)

A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface. - Changhyun Kim; Kye-Hyun Kyung; W.-P. Jeong; J.-S. Kim; Byung-Sik Moon; Joon-Wan Chai; S.-M. Yim; Jung-Hwan Choi; K.-H. Han; C.-J. Park; Hong-Sun Hwang; H. Choi; et al. (IEEE J. Solid State Circuits, 1999)

A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity. - Kyehyun Kyung; Hi-Choon Lee; Ki-Whan Song; Ho-Sung Song; Keewook Jung; Joon-Seo Moon; Byoung-Sul Kim; Sung-Burn Cho; Changhyun Kim; Soo-In Cho (IEEE J. Solid State Circuits, 2001)

A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration. - Changsik Yoo; Kye-Hyun Kyung; Kyunam Lim; Hi-Choon Lee; Joon-Wan Chai; Nak-Won Heo; Dong-Jin Lee; Chang-Hyun Kim (IEEE J. Solid State Circuits, 2004)

1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. - Yongsam Moon; Yong-Ho Cho; Hyun-Bae Lee; Byung-Hoon Jeong; Seok-Hun Hyun; Byungchul Kim; In-Chul Jeong; Seong-Young Seo; Junho Shin; Seok-Woo Choi; Ho-Sung Song; Jung-Hwan Choi; et al. (ISSCC, 2009)

A 159mm2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface. - Hyunggon Kim; Jung-Hoon Park; Ki-Tae Park; Pansuk Kwak; Ohsuk Kwon; Chulbum Kim; Younyeol Lee; Sangsoo Park; Kyungmin Kim; Doohyun Cho; Juseok Lee; Jungho Song; et al. (ISSCC, 2010)

A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking. - Jung-Sik Kim; Chi Sung Oh; Hocheol Lee; Donghyuk Lee; Hyong-Ryol Hwang; Sooman Hwang; Byongwook Na; Joungwook Moon; Jin-Guk Kim; Hanna Park; Jang-Woo Ryu; Kiwon Park; et al. (ISSCC, 2011)

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. - Daeyeal Lee; Ik Joon Chang; Sangyong Yoon; Joonsuc Jang; Dong-Su Jang; Wook-Ghee Hahn; Jong-Yeol Park; Doo-Gon Kim; Chiweon Yoon; Bong-Soon Lim; ByungJun Min; Sung-Won Yun; et al. (ISSCC, 2012)

A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory. - Seung-Hwan Shin; Dong-Kyo Shim; Jaeyong Jeong; Ohsuk Kwon; Sangyong Yoon; Myung-Hoon Choi; Tae-Young Kim; Hyun Wook Park; Hyun-Jun Yoon; Youngsun Song; Yoon-Hee Choi; Sang-Won Shim; et al. (VLSIC, 2012)

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface. - Chulbum Kim; Jinho Ryu; Tae-Sung Lee; Hyunggon Kim; Jaewoo Lim; Jaeyong Jeong; Seonghwan Seo; Hongsoo Jeon; Bokeun Kim; Inyoul Lee; Dooseop Lee; Pansuk Kwak; et al. (IEEE J. Solid State Circuits, 2012)

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH. - Yong-Sung Cho; Il-Han Park; Sangyong Yoon; Nam-Hee Lee; Sang-Hyun Joo; Ki-Whan Song; Kihwan Choi; Jin-Man Han; Kyehyun Kyung; Young-Hyun Jun (IEEE J. Solid State Circuits, 2013)

19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming. - Ki-Tae Park; Jin-Man Han; Dae-Han Kim; Sangwan Nam; Kihwan Choi; Minsu Kim 004; Pansuk Kwak; Doosub Lee; Yoon-Hee Choi; Kyung-Min Kang; Myung-Hoon Choi; Dong-Hun Kwak; et al. (ISSCC, 2014)

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate. - Jae-Woo Im; Woopyo Jeong; Doo-Hyun Kim; Sangwan Nam; Dong-Kyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Youse Kim; Hyun Wook Park; Dong-Hun Kwak; Sang-Won Park; et al. (ISSCC, 2015)

7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip. - Hyun-Jin Kim; Jeong-Don Lim; Jang-Woo Lee; Dae-Hoon Na; Joon-Ho Shin; Chae-Hoon Kim; Seungwoo Yu; Ji-Yeon Shin; Seon-Kyoo Lee; Devraj Rajagopal; Sang-Tae Kim; Kyeong-Tae Kang; et al. (ISSCC, 2015)

Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming. - Ki-Tae Park; Sangwan Nam; Dae-Han Kim; Pansuk Kwak; Doosub Lee; Yoon-Hee Choi; Myung-Hoon Choi; Dong-Hun Kwak; Doo-Hyun Kim; Minsu Kim 004; Hyun Wook Park; Sang-Won Shim; et al. (IEEE J. Solid State Circuits, 2015)

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers. - Dongku Kang; Woopyo Jeong; Chulbum Kim; Doo-Hyun Kim; Yong-Sung Cho; Kyung-Tae Kang; Jinho Ryu; Kyung-Min Kang; Sungyeon Lee; Wandong Kim; Hanjun Lee; Jaedoeg Yu; et al. (ISSCC, 2016)

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate. - Seungjae Lee 001; Jin-Yub Lee; Il-Han Park; Jong-Yeol Park; Sung-Won Yun; Minsu Kim 004; Jong-Hoon Lee; Min-Seok Kim; Kangbin Lee; Taeeun Kim; Byungkyu Cho; Dooho Cho; et al. (ISSCC, 2016)

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate. - Woopyo Jeong; Jae-Woo Im; Doo-Hyun Kim; Sangwan Nam; Dong-Kyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Youse Kim; Hyun Wook Park; Dong-Hun Kwak; Sang-Won Park; et al. (IEEE J. Solid State Circuits, 2016)

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory. - Chulbum Kim; Ji-Ho Cho; Woopyo Jeong; Il-Han Park; Hyun Wook Park; Doo-Hyun Kim; Daewoon Kang; Sunghoon Lee; Ji-Sang Lee; Wontae Kim 004; Jiyoon Park; Yang-Lo Ahn; et al. (ISSCC, 2017)

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers. - Dongku Kang; Woopyo Jeong; Chulbum Kim; Doo-Hyun Kim; Yong-Sung Cho; Kyung-Tae Kang; Jinho Ryu; Kyung-Min Kang; Sungyeon Lee; Wandong Kim; Hanjun Lee; Jaedoeg Yu; et al. (IEEE J. Solid State Circuits, 2017)

A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput. - Seungjae Lee 001; Chulbum Kim; Minsu Kim 004; Sung-Min Joe; Joonsuc Jang; Seungbum Kim; Kangbin Lee; Jisu Kim; Jiyoon Park; Hanjun Lee; Min-Seok Kim; Seonyong Lee; et al. (ISSCC, 2018)

A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory. - Chulbum Kim; Doo-Hyun Kim; Woopyo Jeong; Hyun-Jin Kim; Il-Han Park; Hyun Wook Park; Jong-Hoon Lee; Jiyoon Park; Yang-Lo Ahn; Ji Young Lee; Seungbum Kim; Hyun-Jun Yoon; et al. (IEEE J. Solid State Circuits, 2018)

A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface. - Dongku Kang; Minsu Kim 004; Suchang Jeon; Wontaeck Jung; Jooyong Park; Gyo Soo Choo; Dong-Kyo Shim; Anil Kavala; Seungbum Kim; Kyung-Min Kang; Jiyoung Lee; Kuihan Ko; et al. (ISSCC, 2019)