A fast pump-down VBB generator for sub-1.5-V DRAMs. - Kyeong-Sik Min; Jin-Yong Chung (IEEE J. Solid State Circuits, 2001)

CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. - Kyeong-Sik Min; Young-Hee Kim; Jin-Hong Ahn; Jin-Yong Chung; Takayasu Sakurai (ISCAS (5), 2002)

A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs. - Jae-Kyung Wee; Kyeong-Sik Min; Jong-Tai Park; Sang-Pil Lee; Young-Hee Kim; Tae-Heum Yang; Jong-Doo Joo; Jin-Yong Chung (IEEE J. Solid State Circuits, 2002)

A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications. - Kyeong-Sik Min; Young-Hee Kim; Daejeong Kim; Dong Myeong Kim; Jin-Hong Ahn (ASP-DAC, 2004)

A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs. - Young-Jin Jeon; Joong-Ho Lee; Hyun-Chul Lee; Kyo-Won Jin; Kyeong-Sik Min; Jin-Yong Chung; Hong-June Park (IEEE J. Solid State Circuits, 2004)

Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's. - Kyeong-Sik Min; Kouichi Kanda; Hiroshi Kawaguchi 001; Kenichi Inagaki; Fayez Robert Saliba; Hoon-Dae Choi; Hyun-Young Choi; Daejeong Kim; Dong Myong Kim; Takayasu Sakurai (IEICE Trans. Electron., 2005)

Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD LSIs. - Kyeong-Sik Min; Hun-Dae Choi; H.-Y. Choi; Hiroshi Kawaguchi 001; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs. - Duk-Hyung Lee; Dong-Kone Kwak; Kyeong-Sik Min (VLSI Design, 2007)

A compact HSPICE macromodel of resistive RAM. - Jin-Gu Lee; Dae Hwan Kim; Jaegab Lee; Dong Myong Kim; Kyeong-Sik Min (IEICE Electron. Express, 2007)

Fast-Delay and Low-Power Level Shifter for Low-Voltage Applications. - O-Sam Kwon; Kyeong-Sik Min (IEICE Trans. Electron., 2007)

An Approach for Numerical Analysis of Differential Equation-Based Feeding Point Modeling of Electromagnetic Devices. - Kyeong-Sik Min; Manh-Dat Vu (IEICE Trans. Commun., 2007)

Sense amplifier driving scheme with adaptive delay line for reducing peak current and driving time variations in deep-sub-micron DRAMs. - O-Sam Kwon; Yong-Jin Kwon; Ho-Jun Song; Kyeong-Sik Min (IEICE Electron. Express, 2008)

A Modified Dickson Charge Pump Circuit with High Efficiency and High Output Voltage. - Duk-Hyung Lee; Daejeong Kim; Ho-Jun Song; Kyeong-Sik Min (IEICE Trans. Electron., 2008)

History of Antenna Technology for Mobile Communications in Korea. - Kyeong-Sik Min; Chul-Keun Park; Suk-Youb Kang (IEICE Trans. Commun., 2008)

Comparative Study on Leakage Current of Power-Gated SRAMs for 65-nm, 45-nm, 32-nm Technology Nodes. - Duk-Hyung Lee; Dong-Kone Kwak; Kyeong-Sik Min (J. Comput., 2008)

New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs. - Ji-Hye Bong; Yong-Jin Kwon; Kyeong-Sik Min; Sung-Mo Kang (ISQED, 2009)

Negative charge pump circuit with large output current and high power efficiency. - Ji-Hye Bong; Yong-Jin Kwon; Daejeong Kim; Kyeong-Sik Min (IEICE Electron. Express, 2009)

Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs. - Kwan-Hee Jo; Ji-Hye Bong; Kyeong-Sik Min (IEICE Electron. Express, 2009)

A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs. - Kwan-Hee Jo; Ji-Hye Bong; Kyeong-Sik Min; Sung-Mo Kang (IEICE Electron. Express, 2009)

Sub-1-V-Output CMOS bandgap reference circuit with small area and low power consumption. - Yong-Jin Kwon; Ji-Hye Bong; Dae Hwan Kim; Kyeong-Sik Min (IEICE Electron. Express, 2009)

Memristor models and circuits for controlling Process-VDD-Temperature variations. - Kwan-Hee Jo; Chul-Moon Jung; Kyeong-Sik Min (ASICON, 2011)

Compact and efficient Maximum Power Point Tracking circuit for portable solar battery charger. - Eun-Sub Lee; Chul-Mun Jung; Huan Minh Vo; Kyeong-Sik Min (IEICE Electron. Express, 2011)

Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes. - Huan Minh Vo; Chul-Moon Jung; Eun-Sub Lee; Kyeong-Sik Min (IEICE Electron. Express, 2011)

Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs. - Huan Minh Vo; Chul-Moon Jung; Eun-Sub Lee; Kyeong-Sik Min (IEICE Electron. Express, 2011)

Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits. - Ji-Hye Bong; Kwan-Hee Jo; Kyeong-Sik Min; Sung-Mo Kang (J. Low Power Electron., 2011)

Sunlight-variation-adaptive charge pump circuit with self-reconfiguration for small-scale solar energy harvesting. - Eun-Sub Lee; Jun-Myung Choi; Young-Su Kim; Seok-Jin Ham; Jeong-Heon Kim; Sang-Don Byeon; Kyeong-Sik Min (IEICE Electron. Express, 2012)

Memristor-based cellular nanoscale networks: Theory, circuits, and applications. - Son Ngoc Truong; SangHak Shin; JeaSang Song; Hyun-Sun Mo; Fernando Corinto; Kyeong-Sik Min (ISCAS, 2015)

Live demonstration: Memristor synaptic array with FPGA-implemented neurons for neuromorphic pattern recognition. - Son Ngoc Truong; Khoa Van Pham; Wonsun Yang; Kyeong-Sik Min; Yawar Abbas; Chi Jung Kang (APCCAS, 2016)

Memristor circuits and systems for future computing and bio-inspired information processing. - Son Ngoc Truong; Khoa Van Pham; Wonsun Yang; Kyeong-Sik Min (BioCAS, 2016)

New pulse amplitude modulation for fine tuning of memristor synapses. - Son Ngoc Truong; Khoa Van Pham; Wonsun Yang; Sangho Shin; Ken Pedrotti; Kyeong-Sik Min (Microelectron. J., 2016)

Cellular Nonlinear Networks with Memristor Synapses. - Fernando Corinto; Alon Ascoli; Young-Su Kim; Kyeong-Sik Min (Handbook of Memristor Networks, 2019)

Defect-Tolerant and Energy-Efficient Training of Multi-Valued and Binary Memristor Crossbars for Near-Sensor Cognitive Computing. - Khoa Van Pham; Tien Van Nguyen; Kyeong-Sik Min (ASICON, 2019)

Defect-Tolerant Crossbar Training of Memristor Ternary Neural Networks. - Khoa Van Pham; Tien Van Nguyen; Kyeong-Sik Min (ICECS, 2019)

Non-Ideal Effects of Memristor-CMOS Hybrid Circuits for Realizing Multiple-Layer Neural Networks. - Khoa Van Pham; Kyeong-Sik Min (ISCAS, 2019)

Defect-Resilient Memristor Crossbar of Hierarchical Temporal Memory (HTM) Spatial Pooling for Near-IoT-Sensor Cognitive Computing. - Tien Van Nguyen; Ngoc-Thanh Le; Jiyong An; Kyeong-Sik Min (ICECS, 2020)

Comparative Study on Quantization-Aware Training of Memristor Crossbars for Reducing Inference Power of Neural Networks at The Edge. - Tien Van Nguyen; Jiyong An; Kyeong-Sik Min (IJCNN, 2021)

Neuron Deactivation Scheme for Defect-Tolerant Memristor Neural Networks. - Seokjin Oh; Jiyong An; Kyeong-Sik Min (MOCAST, 2022)

Quantization, training, parasitic resistance correction, and programming techniques of memristor-crossbar neural networks for edge intelligence. - Tien Van Nguyen; Jiyong An; Seokjin Oh; Son Ngoc Truong; Kyeong-Sik Min (Neuromorph. Comput. Eng., 2022)

Hardware-Specific Optimization for Mapping of Convolutional Neural Networks to Memristor Crossbars. - Seokjin Oh; Rina Yoon; Seungmyeong Cho; Kyeong-Sik Min (ASICON, 2023)

Memristor Circuits for Non-Backpropagation Training Algorithm. - Seokjin Oh; Rina Yoon; Seungmyeong Cho; Kyeong-Sik Min (ISOCC, 2023)

Memristor crossbar circuits of unconventional computing for low-power IoT devices. - Rina Yoon; Seokjin Oh; Seungmyeong Cho; Ilpyeong Yoon; Jihwan Mun; Kyeong-Sik Min (APCCAS, 2024)

Assessing the Role of Yarn Placement in Plated Knit Strain Sensors: A Detailed Study of Their Electromechanical Properties and Applicability in Bending Cycle Monitoring. - Youn-Hee Kim; Juwon Jun; You-Kyung Oh; Hee-Ji Choi; Mi-Jung Lee; Kyeong-Sik Min; Sung-Hyon Kim; Hyunseung Lee 004; Ho-Seok Nam; Son Singh; Byoung-Joon Kim; Jaegab Lee (Sensors, 2024)

Optimization of Memristor Crossbar's Mapping Using Lagrange Multiplier Method and Genetic Algorithm for Reducing Crossbar's Area and Delay Time. - Seungmyeong Cho; Rina Yoon; Ilpyeong Yoon; Jihwan Moon 004; Seokjin Oh; Kyeong-Sik Min (Inf., 2024)