A CMOS serial link for fully duplexed data communication. - Kyeongho Lee; Sungjoon Kim; Gijung Ahn; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 1995)

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL. - Sungjoon Kim; Kyeongho Lee; Yongsam Moon; Deog-Kyoon Jeong; Yunho Choi; Hyung Kyu Lim (IEEE J. Solid State Circuits, 1997)

1.04 GBd low EMI digital video interface system using small swing serial link technique. - Kyeongho Lee; Yeshik Shin; Sungjoon Kim; Deog-Kyoon Jeong; Gyudong Kim; Bruce Kim; Victor Da Costa (IEEE J. Solid State Circuits, 1998)

A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. - Yongsam Moon; Jongsang Choi; Kyeongho Lee; Deog-Kyoon Jeong; Min-Kyu Kim (CICC, 1999)

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. - Yongsam Moon; Jongsang Choi; Kyeongho Lee; Deog-Kyoon Jeong; Min-Kyu Kim (IEEE J. Solid State Circuits, 2000)

A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique. - Kyeongho Lee; Joonbae Park; Jeong-Woo Lee; Seung-Wook Lee; Hyung Ki Huh; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2001)

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems. - Yido Koo; Hyungki Huh; Yongsik Cho; Jeongwoo Lee; Joonbae Park; Kyeongho Lee; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2002)

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver. - Kang-Yoon Lee; Seung-Wook Lee; Yido Koo; Hyoung-Ki Huh; Hee-Young Nam; Jeong-Woo Lee; Joonbae Park; Kyeongho Lee; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2003)

Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer. - Hyungki Huh; Yido Koo; Kang-Yoon Lee; Yeonkyeong Ok; Sungho Lee; Daehyun Kwon; Jeongwoo Lee; Joonbae Park; Kyeongho Lee; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2005)

Novel Traffic Measurement Methodology for High Precision Applications Awareness in Multi-gigabit Networks. - Taesang Choi; Sangsik Yoon; Dongwon Kang; Sangwan Kim; Joonkyung Lee; Kyeongho Lee (APNOMS, 2006)

Wire-speed application flow generation in hardware platform for multi-gigabit traffic monitoring. - Taesang Choi; Sangsik Yoon; Dongwon Kang; Sangwan Kim; Joonkyung Lee; Kyeongho Lee (NOMS, 2008)

A Preliminary Study on Human Trust Measurements by EEG for Human-Machine Interactions. - Suh-Yeon Dong; Bo-Kyeong Kim; Kyeongho Lee; Soo-Young Lee (HAI, 2015)

Implicit Shopping Intention Recognition with Eye Tracking Data and Response Time. - Dong-Gun Lee; Kyeongho Lee; Soo-Young Lee (HAI, 2015)

Content addressable memory based binarized neural network accelerator using time-domain signal processing. - Woong Choi; Kwanghyo Jeong; Kyungrak Choi; Kyeongho Lee; Jongsun Park 001 (DAC, 2018)

Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme. - Woong Choi; Kyeongho Lee; Jongsun Park 001 (ISCAS, 2018)

Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme. - Kyeongho Lee; Geon Ko; Jongsun Park 001 (ISCAS, 2019)

Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. - Kyeongho Lee; Jinho Jeong 002; Sungsoo Cheon; Woong Choi; Jongsun Park 001 (DAC, 2020)

A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration. - Kyeongho Lee; Sungsoo Cheon; Joongho Jo; Woong Choi; Jongsun Park 001 (DAC, 2021)

A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge. - Kyeongho Lee; Woong Choi; Jongsun Park 001 (IEEE J. Solid State Circuits, 2021)

A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion. - Hyunchul Park; Kyeongho Lee; Jongsun Park 001 (AICAS, 2022)

Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion. - Kyeongho Lee; Joonhyung Kim; Jongsun Park 001 (ICCAD, 2022)

A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. - Joonhyung Kim; Kyeongho Lee; Jongsun Park 001 (ISLPED, 2022)

Low Area and Low Power Threshold Implementation Design Technique for AES S-Box. - Junhyun Song; Kyeongho Lee; Jongsun Park 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network. - Sungsoo Cheon; Kyeongho Lee; Jongsun Park 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

TP-DCIM: Transposable Digital SRAM CIM Architecture for Energy-Efficient and High Throughput Transformer Acceleration. - Junwoo Park; Kyeongho Lee; Jongsun Park 001 (ICCAD, 2024)

A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations. - Kyeongho Lee; Joonhyung Kim; Jongsun Park 001 (IEEE J. Solid State Circuits, 2024)

A Design Framework of Heterogeneous Approximate DCIM-Based Accelerator for Energy-Efficient NN Processing. - Kyeongho Lee; Hyeyeong Lee; Jongsun Park 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)