Implementation of a RISC microprocessor for programmable logic controllers. - Gab Seon Rho; Kyeonghoon Koo; Naehyuck Chang; Jaehyun Park 005; Yeong-gi Kim; Wook Hyun Kwon (Microprocess. Microsystems, 1995)

Worst-case timing prediction of relay ladder logic by constraint analysis. - Kyeonghoon Koo; Wook Hyun Kwon (RTCSA, 1996)

Architectural design of an RISC processor for programmable logic controllers. - Kyeonghoon Koo; Gab Seon Rho; Wook Hyun Kwon; Jaehyun Park 003; Naehyuck Chang (J. Syst. Archit., 1998)