Reduced Overhead Gate Level Logic Encryption. - Kyle Juretus; Ioannis Savidis (ACM Great Lakes Symposium on VLSI, 2016)

Reducing logic encryption overhead through gate level key insertion. - Kyle Juretus; Ioannis Savidis (ISCAS, 2016)

Physical gate based preamble obfuscation for securing wireless communication. - James Chacko; Kyle Juretus; Marko Jacovic; Cem Sahin; Nagarajan Kandasamy; Ioannis Savidis; Kapil R. Dandekar (ICNC, 2017)

Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security. - Kyle Juretus; Ioannis Savidis (APCCAS, 2018)

Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures. - David Werner; Kyle Juretus; Ioannis Savidis; Mark Hempstead (ICCD, 2018)

Time Domain Sequential Locking for Increased Security. - Kyle Juretus; Ioannis Savidis (ISCAS, 2018)

Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies. - Kyle Juretus; Vaibhav Venugopal Rao; Ioannis Savidis (ACM Great Lakes Symposium on VLSI, 2019)

Increasing the SAT Attack Resiliency of In-Cone Logic Locking. - Kyle Juretus; Ioannis Savidis (ISCAS, 2019)

Securing Wireless Communication via Hardware-Based Packet Obfuscation. - James Chacko; Kyle Juretus; Marko Jacovic; Cem Sahin; Nagarajan Kandasamy; Ioannis Savidis; Kapil R. Dandekar (J. Hardw. Syst. Secur., 2019)

Reducing Logic Locking Key Leakage through the Scan Chain. - Kyle Juretus; Ioannis Savidis (ISCAS, 2020)

Security Vulnerabilities of Obfuscated Analog Circuits. - Vaibhav Venugopal Rao; Kyle Juretus; Ioannis Savidis (ISCAS, 2020)

Physical Layer Encryption for Wireless OFDM Communication Systems. - Marko Jacovic; Kyle Juretus; Nagarajan Kandasamy; Ioannis Savidis; Kapil R. Dandekar (J. Hardw. Syst. Secur., 2020)

Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack. - Kyle Juretus; Ioannis Savidis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Synthesis of Hidden State Transitions for Sequential Logic Locking. - Kyle Juretus; Ioannis Savidis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking. - Kyle Juretus; Ioannis Savidis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Practical Performance of Analog Attack Techniques. - Vaibhav Venugopal Rao; Kyle Juretus; Ioannis Savidis (HOST, 2022)

Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator. - Benjamin J. Lucas; Ali Alwan; Marion Murzello; Yazheng Tu; Pengzhou He; Andrew J. Schwartz; David Guevara; Ujjwal Guin; Kyle Juretus; Jiafeng Xie (IEEE Comput. Archit. Lett., 2022)

Deep Learning Sparse Array Design Using Binary Switching Configurations. - Syed A. Hamza; Kyle Juretus; Moeness G. Amin; Fauzia Ahmad (ICASSP, 2023)

Hidden Costs of Analog Deobfuscation Attacks. - Vaibhav Venugopal Rao; Kyle Juretus; Ioannis Savidis (IEEE Trans. Very Large Scale Integr. Syst., 2023)

PP-HDC: A Privacy-Preserving Inference Framework for Hyperdimensional Computing. - Ruixuan Wang; Wengying Wen; Kyle Juretus; Xun Jiao (DATE, 2024)

Boolean Domain Attack on Corrupt and Correct Based Logic Locking Techniques. - Joseph Madera; Kyle Juretus (ACM Great Lakes Symposium on VLSI, 2024)

DNA: DC Nodal Analysis Attack for Analog Circuits. - Vaibhav Venugopal Rao; Kyle Juretus; Ioannis Savidis (ISCAS, 2024)

On the Roles of Sparse Array Configuration and Weights in Optimum Beamforming. - Syed A. Hamza; Moeness G. Amin; Kyle Juretus (WCNC, 2024)

Deep Learning of the Sparse Array Configurations in Optimum Beamforming. - Kyle Juretus; Moeness G. Amin; Syed A. Hamza (IEEE Trans. Aerosp. Electron. Syst., 2025)

Exploring Hyperdimensional Computing Robustness Against Hardware Errors. - Sizhe Zhang; Kyle Juretus; Xun Jiao (IEEE Trans. Computers, 2025)