LARS: Logically adaptable retention time STT-RAM cache for embedded systems. - Kyle Kuan; Tosiron Adegbija (DATE, 2018)

MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache. - Kyle Kuan; Tosiron Adegbija (ACM Great Lakes Symposium on VLSI, 2019)

SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. - Dhruv Gajaria; Kyle Kuan; Tosiron Adegbija (IGSC, 2019)

Energy and Performance Analysis of STTRAM Caches for Mobile Applications. - Kyle Kuan; Tosiron Adegbija (MCSoC, 2019)

HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. - Kyle Kuan; Tosiron Adegbija (IEEE Trans. Computers, 2019)

A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. - Kyle Kuan; Tosiron Adegbija (ICCD, 2020)

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. - Kyle Kuan; Tosiron Adegbija (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Advancing STTRAM Caches for Runtime Adaptable Energy-Efficient Microarchitectures. - Kyle Kuan (2021)

A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation. - Kyle Kuan; Tosiron Adegbija (ISVLSI, 2022)