A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor. - Jae-Hong Kim; Wun-ki Jung; Seung-hyun Lim; Yu-jin Park; Won-Ho Choi; Yun-Jung Kim; Chang-eun Kang; Jihun Shin; Kyojin Choo; Won-baek Lee; Jin-kyeong Heo; Byung-jo Kim; et al. (ISSCC, 2012)

27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC. - Kyojin David Choo; John Bell; Michael P. Flynn (ISSCC, 2016)

A start-up boosting circuit with 133× speed gain for 2-transistor voltage reference. - Dongkwun Kim; Wanyeong Jung; Sechang Oh 001; Kyojin David Choo; Dennis Sylvester; David T. Blaauw (CICC, 2017)

8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment. - Tae-Kwang Jang; Seokhyeon Jeong; Dongsuk Jeon; Kyojin David Choo; Dennis Sylvester; David T. Blaauw (ISSCC, 2017)

22.6 A fully integrated counter-flow energy reservoir for 70%-efficient peak-power delivery in ultra-low-power systems. - Xiao Wu 002; Kyojin David Choo; Yao Shi 001; Li-Xuan Chuo; Dennis Sylvester; David T. Blaauw (ISSCC, 2017)

A Fully Integrated Counter Flow Energy Reservoir for Peak Power Delivery in Small Form-Factor Sensor Systems. - Xiao Wu 002; Kyojin David Choo; Yao Shi 001; Li-Xuan Chuo; Dennis Sylvester; David T. Blaauw (IEEE J. Solid State Circuits, 2017)

A 2.2 NEF Neural-Recording Amplifier Using Discrete-Time Parametric Amplification. - Tae-Kwang Jang; Jongyup Lim; Kyojin David Choo; Samuel Nason; Jeongsup Lee; Jeongsup Oh; Seokhyeon Jeong; Cynthia A. Chestek; Dennis Sylvester; David T. Blaauw (VLSI Circuits, 2018)

A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector. - Tae-Kwang Jang; Seokhyeon Jeong; Dongsuk Jeon; Kyojin David Choo; Dennis Sylvester; David T. Blaauw (IEEE J. Solid State Circuits, 2018)

A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link. - Shiming Song 002; Kyojin David Choo; Thomas Chen 003; Sunmin Jang; Michael P. Flynn; Zhengya Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Energy-Efficient Low-Noise CMOS Image Sensor with Capacitor Array-Assisted Charge-Injection SAR ADC for Motion-Triggered Low-Power IoT Applications. - Kyojin David Choo; Li Xu 006; Yejoong Kim; Ji-Hwan Seol; Xiao Wu 002; Dennis Sylvester; David T. Blaauw (ISSCC, 2019)

An Adiabatic Sense and Set Rectifier for Improved Maximum-Power-Point Tracking in Piezoelectric Harvesting with 541% Energy Extraction Gain. - Yimai Peng; Kyojin David Choo; Sechang Oh 001; Inhee Lee 001; Tae-Kwang Jang; Yejoong Kim; Jongyup Lim; David T. Blaauw; Dennis Sylvester (ISSCC, 2019)

Energy-Efficient Motion-Triggered IoT CMOS Image Sensor With Capacitor Array-Assisted Charge-Injection SAR ADC. - Kyojin David Choo; Li Xu 006; Yejoong Kim; Ji-Hwan Seol; Xiao Wu 002; Dennis Sylvester; David T. Blaauw (IEEE J. Solid State Circuits, 2019)

An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Sense-and-Set Rectifier. - Yimai Peng; Kyojin David Choo; Sechang Oh 001; Inhee Lee 001; Tae-Kwang Jang; Yejoong Kim; Jongyup Lim; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2019)

3.3 A 0.51nW 32kHz Crystal Oscillator Achieving 2ppb Allan Deviation Floor Using High-Energy-to-Noise-Ratio Pulse Injection. - Li Xu 006; Tae-Kwang Jang; Jongyup Lim; Kyojin David Choo; David T. Blaauw; Dennis Sylvester (ISSCC, 2020)

A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge. - Hyochan An; Siddharth Venkatesan; Sam Schiferl; Tim Wesley; Qirui Zhang 001; Jingcheng Wang; Kyojin Choo; Shiyu Liu; Bowen Liu 001; Ziyun Li; Hengfei Zhong; Luyao Gong; et al. (VLSI Circuits, 2020)

Sample and Average Common-Mode Feedback in a 101 nW Acoustic Amplifier. - Rohit Rothe; Sechang Oh 001; Kyojin David Choo; Seokhyeon Jeong; Minchang Cho; Dennis Sylvester; David T. Blaauw (VLSI Circuits, 2020)

14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC. - Kyojin Choo; Hyochan An; Dennis Sylvester; David T. Blaauw (ISSCC, 2021)

A 192 nW 0.02 Hz High Pass Corner Acoustic Analog Front-End with Automatic Saturation Detection and Recovery. - Rohit Rothe; Minchang Cho; Kyojin Choo; Seokhyeon Jeong; Dennis Sylvester; David T. Blaauw (VLSI Circuits, 2021)

An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks. - Hyochan An; Sam Schiferl; Siddharth Venkatesan; Tim Wesley; Qirui Zhang 001; Jingcheng Wang; Kyojin Choo; Shiyu Liu; Bowen Liu 001; Ziyun Li; Luyao Gong; Hengfei Zhong; et al. (IEEE J. Solid State Circuits, 2021)

Reference Oversampling PLL Achieving -256-dB FoM and -78-dBc Reference Spur. - Ji-Hwan Seol; Kyojin Choo; David T. Blaauw; Dennis Sylvester; Taekwang Jang (IEEE J. Solid State Circuits, 2021)

A 184nW, 121µg/√Hz Noise Floor Triaxial MEMS Accelerometer with Integrated CMOS Readout Circuit and Variation-Compensated High Voltage MEMS Biasing. - Yimai Peng; Seokhyeon Jeong; Kyojin Choo; Yejoong Kim; Li-Yu Chen; Rohit Rothe; Li Xu 006; Ilya Gurin; Omid Oliaei; Vadim Tsinker; Stephen Bart; Peter Hartwell; et al. (VLSI Technology and Circuits, 2022)

A Delta Sigma-Modulated Sample and Average Common-Mode Feedback Technique for Capacitively Coupled Amplifiers in a 192-nW Acoustic Analog Front-End. - Rohit Rothe; Minchang Cho; Kyojin Choo; Seokhyeon Jeong; Sechang Oh 001; Jungho Lee; Dennis Sylvester; David T. Blaauw (IEEE J. Solid State Circuits, 2022)

A 510-pW 32-kHz Crystal Oscillator With High Energy-to-Noise-Ratio Pulse Injection. - Li Xu 006; Taekwang Jang; Jongyup Lim; Kyojin David Choo; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2022)

A 0.000261 mm2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS. - Chan-Ho Kye; Kyojin Choo (A-SSCC, 2023)

An Ultralow-Power Triaxial MEMS Accelerometer With High-Voltage Biasing and Electrostatic Mismatch Compensation. - Yimai Peng; Seokhyeon Jeong; Kyojin Choo; Yejoong Kim; Li-Yu Chen; Rohit Rothe; Li Xu 006; Ilya Gurin; Omid Oliaei; Matthew J. Thompson; Stephen Bart; Peter Hartwell; et al. (IEEE J. Solid State Circuits, 2024)

Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC. - Chan-Ho Kye; Yu-Jin Byeon; Kyojin Choo; Min-Seong Choo (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)