A Novel HV-NPN ESD Protection Device with Buried Floating P-Type Implant. - Jie Jack Zeng; Ruchil Jain; Kyong Jin Hwang; Robert Gauthier 002 (IRPS, 2019)

Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology. - Kyong Jin Hwang; Sagar Premnath Karalkar; Vishal Ganesan; Sevashanmugam Marimuthu; Alban Zaka; Tom Herrmann; Bhoopendra Singh; Robert Gauthier 002 (IRPS, 2020)

Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp. - Sagar Premnath Karalkar; Vishal Ganesan; Milova Paul; Kyong Jin Hwang; Robert Gauthier 002 (IRPS, 2021)