Avoiding noise frequency interference with binary phase pulse driving and CDS for capacitive TSP controller. - Yong-Sung Ahn; Taek-Joon Ahn; Kyongsu Lee; Jin-Ku Kang (IEICE Electron. Express, 2014)

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS. - Kyongsu Lee; Youngjin Kim; Kyung-Sub Son; Sangmin Lee; Jin-Ku Kang (IEICE Electron. Express, 2014)

Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS. - Kyongsu Lee; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2014)

On-chip jitter tolerance measurement technique for CDR circuits. - Kyung-Sub Son; Kyongsu Lee; Jin-Ku Kang (ISCAS, 2015)

Precise time-difference repetition for TDC with delay mismatch cancelling scheme. - In-Seok Kong; Kyung-Sub Son; Kyongsu Lee; Jin-Ku Kang (IEICE Electron. Express, 2015)

A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector. - Nguyen Huu Tho; Kyung-Sub Son; Kyongsu Lee; Jin-Ku Kang (ISOCC, 2016)

A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling. - Kyongsu Lee; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 143nW Glucose-Monitoring Smart Contact Lens IC with a Dual-Mode Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission Using a Single Loop Antenna. - Cheonhoo Jeon; Jahyun Koo 001; Kyongsu Lee; Su-Kyoung Kim; Sei Kwang Hahn; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (VLSI Circuits, 2019)

A 2.5Gbps Transceiver and Channel Architecture for High-Speed Automotive Communication System. - Kyongsu Lee; Jae-Yoon Sim (IEICE Trans. Electron., 2019)

High-speed transceiver network for in-vehicle communication system. - Kyongsu Lee; Jae-Yoon Sim (ISOCC, 2020)

A Smart Contact Lens Controller IC Supporting Dual-Mode Telemetry With Wireless-Powered Backscattering LSK and EM-Radiated RF Transmission Using a Single-Loop Antenna. - Cheonhoo Jeon; Jahyun Koo 001; Kyongsu Lee; Minseob Lee; Su-Kyoung Kim; Sangbaie Shin; Sei Kwang Hahn; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2020)

Design and Analysis of a Low-Power Ternary SRAM. - Youngchang Choi; Sunmean Kim; Kyongsu Lee; Seokhyeong Kang (ISCAS, 2021)

Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing. - Minjeong Choi; Youngchang Choi; Kyongsu Lee; Seokhyeong Kang (DAC, 2023)

MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors. - Youngchang Choi; Minjeong Choi; Kyongsu Lee; Seokhyeong Kang (DATE, 2023)

Trans-Net: Knowledge-Transferring Analog Circuit Optimizer with a Netlist-Based Circuit Representation. - Ho-Jin Lee; Kyeong-Jun Lee; Youngchang Choi; Kyongsu Lee; Seokhyeong Kang; Jae-Yoon Sim (DATE, 2024)

A 246-fJ/b 13.3-Tb/s/mm Single-Ended Current-Mode Transceiver with Crosstalk Cancellation for Shield-Less Short-Reach Interconnect. - Jaeho Lee; Kyongsu Lee; Jae-Yoon Sim; Seon-Kyoo Lee (VLSI Technology and Circuits, 2024)

MA-Opt: Reinforcement Learning-Based Analog Circuit Optimization Using Multi-Actors. - Youngchang Choi; Sejin Park 001; Minjeong Choi; Kyongsu Lee; Seokhyeong Kang (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

PC-Opt: Partition and Conquest-based Optimizer using Multi-Agents for Complex Analog Circuits. - Youngchang Choi; Sejin Park 001; Ho-Jin Lee; Kyongsu Lee; Jae-Yoon Sim; Seokhyeong Kang (ASP-DAC, 2025)