Interconnect and communication synthesis for distributed register-file microarchitecture. - Kyoung-Hwan Lim; YongHwan Kim; Taewhan Kim (IET Comput. Digit. Tech., 2009)

An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. - Kyoung-Hwan Lim; Taewhan Kim (ASP-DAC, 2011)

Clock design techniques considering circuit reliability. - YongHwan Kim; Minseok Kang; Kyoung-Hwan Lim; Sangdo Park; Deokjin Joo; Taewhan Kim 001 (ISOCC, 2011)

An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs. - Kyoung-Hwan Lim; Deokjin Joo; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)