A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems. - Young-Jae Cho; Kyung-Hoon Lee; Hee-Cheol Choi; Young-Ju Kim; Kyoung-Jun Moon; Seung-Hoon Lee 006; Seok-Bong Hyun; Seong-Su Park (APCCAS, 2006)

A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling. - Kang-Jin Lee; Kyoung-Jun Moon; Kwang-Sung Ma; Kyoung-Ho Moon; Jae-Whui Kim (CICC, 2008)

A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers. - Young-Ju Kim; Hee-Cheol Choi; Kyung-Hoon Lee; Gil-Cho Ahn; Seung-Hoon Lee 006; Ju-Hwa Kim; Kyoung-Jun Moon; Michael Choi; Kyoung-Ho Moon; Ho-Jin Park; Byeong-Ha Park (CICC, 2009)

A 10b 120MS/s 45nm CMOS ADC using A re-configurable three-stage switched op-amp. - Young-Ju Kim; Kyung-Hoon Lee; Seung-Hak Ji; Yi-Gi Kwon; Seung-Hoon Lee 006; Kyoung-Jun Moon; Michael Choi; Ho-Jin Park; Byeong-Ha Park (CICC, 2010)

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS. - Kyoung-Jun Moon; Dong-Shin Jo; Wan Kim; Michael Choi; Hyungjong Ko; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2019)

An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers. - Dong-Ryeol Oh; Kyoung-Jun Moon; Won-Mook Lim; Ye-Dam Kim; Eun-Ji An; Seung-Tak Ryu (VLSI Circuits, 2020)

A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC. - Kyoung-Jun Moon; Dong-Ryeol Oh; Michael Choi; Seung-Tak Ryu (IEEE Trans. Circuits Syst., 2020)

An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS. - Dong-Ryeol Oh; Kyoung-Jun Moon; Won-Mook Lim; Ye-Dam Kim; Eun-Ji An; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2021)

A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET. - Kyoung-Jun Moon; Dong-Ryeol Oh; Young-Hyo Park; Kyung-Hoon Lee; Sun-Jae Park; Sung-No Lee; Hee-Chang Hwang; Hyo-Chul Shin; Young-Jae Cho; Michael Choi; Jongshin Shin (VLSI Technology and Circuits, 2022)