A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process. - Kyoung-Ub Cho; Joonho Gil; Chulhyun Park; Kyu-Jin Cho; Jaewoo Shin; Eun Seong Kim; Yun Seong Eo; Ramesh Harjani; Nam-Young Kim; Taehyoun Oh (IEEE Access, 2024)