A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping. - Sang-Hye Chung; Kyu-Dong Hwang; Won-Young Lee; Lee-Sup Kim (ISCAS, 2010)

An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages. - Kyu-Dong Hwang; Lee-Sup Kim (ISCAS, 2010)

A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposer. - Hyo-Eun Kim; Jae-Sung Yoon; Kyu-Dong Hwang; Young-Jun Kim 001; Jun-Seok Park; Lee-Sup Kim (ISSCC, 2011)

A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme. - Won-Young Lee; Kyu-Dong Hwang; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Reconfigurable Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer. - Hyo-Eun Kim; Jae-Sung Yoon; Kyu-Dong Hwang; Young-Jun Kim 001; Jun-Seok Park; Lee-Sup Kim (IEEE Trans. Circuits Syst. Video Technol., 2012)

A 6.5-Gb/s 1-mW/Gb/s/CH Simple Capacitive Crosstalk Compensator in a 130-nm Process. - Kyu-Dong Hwang; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 5 Gbps 1.6 mW/G bps/CH Adaptive Crosstalk Cancellation Scheme With Reference-less Digital Calibration and Switched Termination Resistors for Single-Ended Parallel Interface. - Kyu-Dong Hwang; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications. - Kyu-Dong Hwang; Boram Kim; Sang-Yeon Byeon; Kyu-Young Kim; Dae-Han Kwon; Hyun-Bae Lee; Geun-Il Lee; Sang-Sic Yoon; Jin-Youp Cha; Soo-Young Jang; Seung-Hun Lee; Yongsuk Joo; et al. (ISSCC, 2018)

A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer. - Jae-Woo Park; Dongsuk Kang; Injae Park; Minsu Park; Xuefan Jin; Kyu-Dong Hwang; Dae-Han Kwon; Jung-Hoon Chun (A-SSCC, 2021)

A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. - Seong Ju Lee; Kyu-Young Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dong Yoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; Nahsung Kim; et al. (ISSCC, 2022)

A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer. - Dongsuk Kang; Jae-Woo Park; Injae Park; Minsu Park; Xuefan Jin; Kyu-Dong Hwang; Dae-Han Kwon; Jung-Hoon Chun (IEEE J. Solid State Circuits, 2022)

A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application. - Dae-Han Kwon; Seongju Lee; Kyuyoung Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dongyoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; et al. (IEEE J. Solid State Circuits, 2023)