An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS). - Kyu-Hyoun Kim; Kwyro Lee; Tae-Sung Jung; Kang-Deog Suh (IEEE J. Solid State Circuits, 1998)

Low-power dynamic termination scheme using NMOS diode clamping. - Dong-Ho Shin; Young-Min Lee; Kyu-Hyoun Kim; Kwyro Lee (IEEE J. Solid State Circuits, 1999)

An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. - Kyu-Hyoun Kim; Uksong Kang; Hoeju Chung; Dukha Park; Woo-Seop Kim; Young-Chan Jang; Moon-Sook Park; Hoon Lee; Jinyoung Kim; Jung Sunwoo; Hwan-Wook Park; Hyun-Kyung Kim; et al. (ISSCC, 2006)

A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter. - Kyu-Hyoun Kim; Young-Soo Sohn; Chan-Kyoung Kim; Moon-Sook Park; Dong-Jin Lee; Woo-Seop Kim; Changhyun Kim (IEEE J. Solid State Circuits, 2006)

A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. - Churoo Park; Hoeju Chung; Yun-Sang Lee; Jaekwan Kim 003; JaeJun Lee; Moo Sung Chae; Dae-Hee Jung; Sung-Ho Choi; Seung-young Seo; Taek-Seon Park; Jun-Ho Shin; Jin-Hyung Cho; et al. (IEEE J. Solid State Circuits, 2006)

A Second Order Mixed-Mode Charge Pump Scheme for Low Phase/Duty Error and Low Power Consumption. - Kyu-Hyoun Kim; In-Young Chung (IEICE Trans. Electron., 2007)

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. - Kyu-Hyoun Kim; Hoeju Chung; Woo-Seop Kim; Moon-Sook Park; Young-Chan Jang; Jinyoung Kim; Hwan-Wook Park; Uksong Kang; Paul W. Coteus; Joo-Sun Choi; Changhyun Kim (IEEE J. Solid State Circuits, 2007)

A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator. - Kyu-Hyoun Kim; Paul W. Coteus; Daniel M. Dreps; Seongwon Kim; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2008)

A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. - Kyu-Hyoun Kim; Daniel M. Dreps; Frank D. Ferraiolo; Paul W. Coteus; Seongwon Kim; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2009)

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. - Janani Mukundan; Hillery C. Hunter; Kyu-Hyoun Kim; Jeffrey Stuecheli; José F. Martínez (ISCA, 2013)

Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor. - Bharat Sukhwani; Thomas Roewer; Charles L. Haymes; Kyu-Hyoun Kim; Adam J. McPadden; Daniel M. Dreps; Dean Sanner; Jan van Lunteren; Sameh W. Asaad (MICRO, 2017)

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads. - Seokin Hong; Prashant Jayaprakash Nair; Bülent Abali; Alper Buyuktosunoglu; Kyu-Hyoun Kim; Michael B. Healy (MICRO, 2018)

Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. - Saravanan Sethuraman; Venkata Kalyan Tavva; Karthick Rajamani; Chitra K. Subramanian; Kyu-Hyoun Kim; Hillery C. Hunter; M. B. Srinivas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

Session 25 Overview: DRAM Memory Subcommittee. - Dong-Uk Lee; Bor-Doou Rong; Kyu-Hyoun Kim (ISSCC, 2021)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)

A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS. - Ankur Agrawal; Monodeep Kar; Kyu-Hyoun Kim; Sergey V. Rylov; Jinwook Jung; Seiji Munetoh; Kohji Hosokawa; Xin Zhang 025; Bahman Hekmatshoartabari; Fabio Carta; Martin Cochet; Robert Casatuta; et al. (VLSI Technology and Circuits, 2023)

Mixed-Signal Dot-Product Processor with Switched-Capacitors for Machine Learning. - Kyu-Hyoun Kim; Mingu Kang (ICEIC, 2024)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)