An MTCMOS design methodology and its application to mobile computing. - Hyo-Sig Won; Kyo-Sun Kim; Kwang-Ok Jeong; Ki-Tae Park; Kyu-Myung Choi; Jeong-Taek Kong (ISLPED, 2003)

Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design. - Chulho Shin; Young-Taek Kim; Eui-Young Chung; Kyu-Myung Choi; Jeong-Taek Kong; Soo-Kwan Eo (DATE, 2004)

Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture. - Young-Taek Kim; Taehun Kim; Youngduk Kim; Chulho Shin; Eui-Young Chung; Kyu-Myung Choi; Jeong-Taek Kong; Soo-Kwan Eo (DATE, 2005)

PowerViP: Soc power estimation framework at transaction level. - Ikhwan Lee; Hyunsuk Kim; Peng Yang; Sungjoo Yoo; Eui-Young Chung; Kyu-Myung Choi; Jeong-Taek Kong; Soo-Kwan Eo (ASP-DAC, 2006)

Worst case execution time analysis for synthesized hardware. - Jun-hee Yoo; Xingguang Feng; Kiyoung Choi; Eui-Young Chung; Kyu-Myung Choi (ASP-DAC, 2006)

Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study. - Sungpack Hong; Sungjoo Yoo; Sheayun Lee; Sangwoo Lee; Hye Jeong Nam; Bum-Seok Yoo; Jaehyung Hwang; Donghyun Song; Janghwan Kim; Jeongeun Kim; HoonSang Jin; Kyu-Myung Choi; et al. (CODES+ISSS, 2006)

A systematic IP and bus subsystem modeling for platform-based system design. - Junhyung Um; Woo-Cheol Kwon; Sungpack Hong; Young-Taek Kim; Kyu-Myung Choi; Jeong-Taek Kong; Soo-Kwan Eo; Taewhan Kim 001 (DATE, 2006)

Runtime distribution-aware dynamic voltage scaling. - Sungpack Hong; Sungjoo Yoo; HoonSang Jin; Kyu-Myung Choi; Jeong-Taek Kong; Soo-Kwan Eo (ICCAD, 2006)

An industrial perspective of power-aware reliable SoC design. - Soo-Kwan Eo; Sungjoo Yoo; Kyu-Myung Choi (ASP-DAC, 2008)

A practical approach of memory access parallelization to exploit multiple off-chip DDR memories. - Woo-Cheol Kwon; Sungjoo Yoo; Sung-Min Hong; Byeong Min; Kyu-Myung Choi; Soo-Kwan Eo (DAC, 2008)

Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution. - Sungpack Hong; Sungjoo Yoo; Byeong Bin; Kyu-Myung Choi; Soo-Kwan Eo; Taehwan Kim 007 (DATE, 2008)

An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication. - Woo-Cheol Kwon; Sung-Min Hong; Sungjoo Yoo; Byeong Min; Kyu-Myung Choi; Soo-Kwan Eo (DATE, 2008)

45nm Low-power Embedded Pseudo-SRAM with ECC-based Auto-adjusted Self-refresh Scheme. - Suk-Soo Pyo; Cheol-Ha Lee; Gyun-Hong Kim; Kyu-Myung Choi; Young-Hyun Jun; Bai-Sun Kong (ISCAS, 2009)

An industrial perspective of 3D IC integration technology: from the viewpoint of design technology. - Kyu-Myung Choi (ASP-DAC, 2010)

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. - Youngsoo Shin; Jun Seomun; Kyu-Myung Choi; Takayasu Sakurai (ACM Trans. Design Autom. Electr. Syst., 2010)

Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS. - Hyung-Ock Kim; Bong Hyun Lee; Jong-Tae Kim; Jung Yun Choi; Kyu-Myung Choi; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2010)

13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications. - Taejoong Song; Woojin Rim; Jonghoon Jung; Giyong Yang; Jaeho Park; Sunghyun Park 003; Kang-Hyun Baek; Sanghoon Baek; Sang-Kyu Oh; Jinsuk Jung; Sungbong Kim; Gyu-Hong Kim; et al. (ISSCC, 2014)

A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications. - Taejoong Song; Woojin Rim; Jonghoon Jung; Giyong Yang; Jaeho Park; Sunghyun Park 003; Yongho Kim; Kang-Hyun Baek; Sanghoon Baek; Sang-Kyu Oh; Jinsuk Jung; Sungbong Kim; et al. (IEEE J. Solid State Circuits, 2015)

Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion. - Kyeongrok Jo; Seyong Ahn; Taewhan Kim 001; Kyu-Myung Choi (ASP-DAC, 2018)

SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage. - Taehwan Kim 007; Kwangok Jeong; Taewhan Kim 001; Kyu-Myung Choi (ISVLSI, 2019)

Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization. - Kyeongrok Jo; Seyong Ahn; Jungho Do; Taejoong Song; Taewhan Kim 001; Kyu-Myung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes. - Jeongwoo Heo; Kwangok Jeong; Taewhan Kim 001; Kyu-Myung Choi (ASP-DAC, 2020)

SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage. - Taehwan Kim 007; Kwangok Jeong; Jungyun Choi; Taewhan Kim 001; Kyu-Myung Choi (Integr., 2020)

DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. - Kyungjoon Chang; Jaehoon Ahn; Heechun Park; Kyu-Myung Choi; Taewhan Kim 001 (DATE, 2023)

Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. - Handong Cho; Hyunbae Seo; Sehyeon Chung; Kyu-Myung Choi; Taewhan Kim 001 (DATE, 2024)

BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost. - Chanhee Jeon; Doyeon Won; Jaewan Yang; Kyu-Myung Choi; Taewhan Kim 001 (DATE, 2024)