Improved Test Generation for High-Activity Circuits. - Kewal K. Saluja; Kyuchull Kim (IEEE Des. Test Comput., 1990)

On fault deletion problem in concurrent fault simulation for synchronous sequential circuits. - Kyuchull Kim; Kewal K. Saluja (VTS, 1992)

CCSTG: an efficient test pattern generator for sequential circuits. - Kyuchull Kim; Kewal K. Saluja (VTS, 1993)

Fast computation of MISR signatures. - Manoj Franklin; Kewal K. Saluja; Kyuchull Kim (VLSI Design, 1995)

HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits. - Kyuchull Kim; Kewal K. Saluja (VLSI Design, 1996)

Low-Area Wrapper Cell Design for Hierarchical SoC Testing. - Kyuchull Kim; Kewal K. Saluja (J. Electron. Test., 2009)