A fast two-pass HDL simulation with on-demand dump. - Kyuho Shim; Young-Rae Cho; Namdo Kim; Hyuncheol Baik; Kyungkuk Kim; Dusung Kim; Jaebum Kim; Byeongun Min; Kyumyung Choi; Maciej J. Ciesielski; Seiyang Yang (ASP-DAC, 2008)

Temporal parallel gate-level timing simulation. - Dusung Kim; Maciej J. Ciesielski; Kyuho Shim; Seiyang Yang (HLDVT, 2008)

Simulation Acceleration with HW Re-Compilation Avoidance. - Kyuho Shim; Kesava R. Talupuru; Maciej J. Ciesielski; Seiyang Yang (VLSI Design, 2008)

Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. - Dusung Kim; Maciej J. Ciesielski; Kyuho Shim; Seiyang Yang (DATE, 2011)

System-level simulation acceleration for architectural performance analysis using hybrid virtual platform system. - Kyuho Shim; Woojoo Kim; Kwang-Hyun Cho; Byeong Min (ISOCC, 2012)