An Open-source Framework for Autonomous SoC Design with Analog Block Generation. - Tutu Ajayi; Sumanth Kamineni; Yaswanth K. Cherivirala; Morteza Fayazi; Kyumin Kwon; Mehdi Saligane; Shourya Gupta; Chien-Hen Chen; Dennis Sylvester; David T. Blaauw; Ronald G. Dreslinski; Benton H. Calhoun; et al. (VLSI-SOC, 2020)

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. - Tutu Ajayi; Sumanth Kamineni; Morteza Fayazi; Yaswanth K. Cherivirala; Kyumin Kwon; Shourya Gupta; Wenbo Duan; Jeongsup Lee; Chien-Hen Chen; Mehdi Saligane; Dennis Sylvester; David T. Blaauw; et al. (VLSI-SoC (Selected Papers), 2020)

An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer. - Seungjong Lee; Taewook Kang; Seungheun Song; Kyumin Kwon; Michael P. Flynn (VLSI Technology and Circuits, 2022)

A Power-Efficient Brain-Machine Interface System With a Sub-mw Feature Extraction and Decoding ASIC Demonstrated in Nonhuman Primates. - Hyochan An; Samuel R. Nason-Tomaszewski; Jongyup Lim; Kyumin Kwon; Matthew S. Willsey; Parag G. Patil; Hun-Seok Kim; Dennis Sylvester; Cynthia A. Chestek; David T. Blaauw (IEEE Trans. Biomed. Circuits Syst., 2022)

Synthesizable ADPLL Generator: From Specification to GDS. - Kyumin Kwon; David D. Wentzloff (SMACD, 2023)

An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer. - Seungjong Lee; Taewook Kang; Seungheun Song; Kyumin Kwon; Michael P. Flynn (IEEE J. Solid State Circuits, 2023)

PLL Fractional Spur's Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter. - Kyumin Kwon; Omar A. B. Abdelatty; David D. Wentzloff (IEEE J. Solid State Circuits, 2023)

A 1/10 DTC Range Reduction Technique in a Fractional-N MDLL Using a Reference Triggered Ring Oscillator. - Kyumin Kwon; Yaswanth Kumar Cherivirala; David D. Wentzloff (ISCAS, 2025)