Exploration of Area and Performance Optimized Datapath Design Using Realistic Cost Metrics. - Kyumyung Choi; Steven P. Levitan (ISCAS, 1995)

A flexible datapath allocation method for architectural synthesis. - Kyumyung Choi; Steven P. Levitan (ACM Trans. Design Autom. Electr. Syst., 1999)

A fast two-pass HDL simulation with on-demand dump. - Kyuho Shim; Young-Rae Cho; Namdo Kim; Hyuncheol Baik; Kyungkuk Kim; Dusung Kim; Jaebum Kim; Byeongun Min; Kyumyung Choi; Maciej J. Ciesielski; Seiyang Yang (ASP-DAC, 2008)

Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net. - Kyeonghyeon Baek; Hyunbum Park; Suwan Kim; Kyumyung Choi; Taewhan Kim 001 (ICCAD, 2022)

Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon. - Jeongwoo Heo; Kwangok Jeong; Jungyun Choi; Taewhan Kim 001; Kyumyung Choi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes. - Sehyeon Chung; Hyunbae Seo; Handong Cho; Kyumyung Choi; Taewhan Kim 001 (ICCAD, 2024)

Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model. - Suwan Kim; Hyunbum Park; Kyeonghyeon Baek; Kyumyung Choi; Taewhan Kim 001 (ISPD, 2024)

DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement. - Jaehoon Ahn; Kyungjoon Chang; Kyumyung Choi; Taewhan Kim 001; Heechun Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes With Consolidated Practical Applicability and Sustainability. - Hyunbum Park; Kyeonghyeon Baek; Suwan Kim; Kyumyung Choi; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)