Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model. - Seidai Takeda; Kyundong Kim; Hiroshi Nakamura; Kimiyoshi Usami (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A novel power-gating scheme utilizing data retentiveness on caches. - Kyundong Kim; Seidai Takeda; Shinobu Miwa; Hiroshi Nakamura (ACM Great Lakes Symposium on VLSI, 2012)

Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches. - Kyundong Kim; Seidai Takeda; Shinobu Miwa; Hiroshi Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. - Hiroki Noguchi; Kumiko Nomura; Keiko Abe; Shinobu Fujita; Eishi Arima; Kyundong Kim; Takashi Nakada; Shinobu Miwa; Hiroshi Nakamura (DATE, 2013)