Design of low-error fixed-width modified booth multiplier. - Kyung-Ju Cho; Kwang-Chul Lee; Jin-Gyun Chung; Keshab K. Parhi (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Hardware Efficient QR Decomposition for GDFE. - Kyung-Ju Cho; Yi-Nan Xu; Jin-Gyun Chung (SiPS, 2007)

Adaptive Error Compensation for Low Error Fixed-Width Squarers. - Kyung-Ju Cho; Jin-Gyun Chung (IEICE Trans. Inf. Syst., 2007)

Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients. - Yong-Eun Kim; Kyung-Ju Cho; Jin-Gyun Chung (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter. - Kyung-Ju Cho; Ji-Suk Park; Byeong-Kuk Kim; Jin-Gyun Chung; Keshab K. Parhi (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Constant multiplier design using specialized bit pattern adders. - Kyung-Ju Cho; Suhyun Jo; Yong-Eun Kim; Yi-Nan Xu; Jin-Gyun Chung (ICECS, 2008)

Implementation of FlexRay communication controller protocol with application to a robot system. - Yi-Nan Xu; Yong-Eun Kim; Kyung-Ju Cho; Jin-Gyun Chung; Myoung-Seob Lim (ICECS, 2008)

Implementation of FlexRay CC and BG Protocols with Application to a Robot System. - Yinan Xu; Hyunsoo Kang; Yongeun Kim; Kyungju Cho; Jingyun Chung (MSV, 2008)

CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups. - Yong-Eun Kim; Kyung-Ju Cho; Jin-Gyun Chung; Xinming Huang 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Fixed-Width Group CSD Multiplier Design. - Yong-Eun Kim; Kyung-Ju Cho; Jin-Gyun Chung; Xinming Huang 001 (IEICE Trans. Inf. Syst., 2010)

Implementation of FlexRay CC and BG protocols with application to a robot system. - Yi-Nan Xu; Yong-Eun Kim; Kyung-Ju Cho; Jin-Gyun Chung; Xinming Huang 001 (Int. J. Comput. Aided Eng. Technol., 2010)

Fixed-Width Modified Booth Multiplier Design Based on Error Bound Analysis. - Kyung-Ju Cho; Jin-Gyun Chung; Hwan-Yong Kim; Gwang-Jun Kim; Dae-Ik Kim; Yong-Kab Kim (FGIT-MulGraB (2), 2011)

A memory size reduction method of pipelined IFFT processor for OFDM systems. - In-Gul Jang; Kyung-Ju Cho (IEICE Electron. Express, 2011)

Efficient IFFT architecture design for OFDM applications. - In-Gul Jang; Dae-Ho Kim; Ho-Yun Yi; Jin-Gyun Chung; Kyung-Ju Cho (ISOCC, 2012)

Efficient unsigned squarer design techniques. - Kyung-Ju Cho (IEICE Electron. Express, 2012)

Memory Size Reduction Technique of SDF IFFT Architecture for OFDM-Based Applications. - In-Gul Jang; Kyung-Ju Cho; Yong-Eun Kim; Jin-Gyun Chung (IEICE Trans. Commun., 2012)

Memory efficient IFFT design for OFDM-based applications. - In-Gul Jang; Kyung-Ju Cho; Hwan-Yong Kim; Jin-Gyun Chung (IEICE Electron. Express, 2013)

Memory efficient DIT-based SDF IFFT for OFDM systems. - Ho-Yun Lee; Jun-Ho Kim; In-Gul Jang; Kyung-Ju Cho; Jin-Gyun Chung (IEICE Electron. Express, 2014)

Low latency IFFT design for 3GPP LTE. - Yeon-Jin Kim; Zhe-Yan Piao; Jin-Gyun Chung; In-Gul Jang; Kyung-Ju Cho (ISOCC, 2016)

Low-latency and memory-efficient SDF IFFT processor design for 3GPP LTE. - Yeon-Jin Kim; In-Gul Jang; Kyung-Ju Cho; Jin-Gyun Chung (IEICE Electron. Express, 2017)